lh5164az8 Sharp Microelectronics of the Americas, lh5164az8 Datasheet

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lh5164az8

Manufacturer Part Number
lh5164az8
Description
Manufacturer
Sharp Microelectronics of the Americas
Datasheet
LH5164AZ8
FEATURES
8,192
Access time:
Power consumption:
Operating voltage range:
Wide operating temperature range:
Fully-static operation
TTL compatible I/O
Three-state outputs
Package: 28-pin, 450-mil SOP
200 ns (V
Operating:
Standby (to 60 C):
Data hold
3.0 V to 3.6 V
-30 to 60 C
60 mW (MAX.) @ 3 V
3 W (MAX.) @ 3 V
0.6 A (V
8 bit organization
CC
CC
= 3.0 V MAX.)
= 3 V, T
A
= 60 C)
DESCRIPTION
8,192
process technology.
PIN CONNECTIONS
The LH5164AZ8 is a static RAM organized as
28-PIN SOP
Figure 1. Pin Connections for SOP Package
8 bits. It is fabricated using silicon-gate CMOS
CMOS 64K (8K
GND
I/O
I/O
I/O
A
NC
A
A
A
A
A
A
A
A
12
1
7
4
0
2
3
6
5
3
2
1
10
12
13
14
11
2
3
4
5
6
7
8
9
1
16
28
27
26
25
24
23
22
20
19
18
17
15
21
8) Static RAM
CE
CE
A
A
A
OE
A
I/O
I/O
I/O
I/O
I/O
V
WE
8
9
11
CC
10
2
1
8
7
6
5
4
TOP VIEW
5164AZ8-1
1

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lh5164az8 Summary of contents

Page 1

... Operating voltage range: 3 3.6 V Wide operating temperature range: - Fully-static operation TTL compatible I/O Three-state outputs Package: 28-pin, 450-mil SOP CMOS 64K (8K DESCRIPTION The LH5164AZ8 is a static RAM organized as 8,192 8 bits fabricated using silicon-gate CMOS process technology. PIN CONNECTIONS 28-PIN SOP ...

Page 2

... Output Enable input 2 MEMORY ARRAY (256 x 256) COLUMN I/O CIRCUITS COLUMN SELECT COLUMN ADDRESS BUFFERS Figure 2. LH5164AZ8 Block Diagram SIGNAL I GND NC CMOS 64K (8K 8) Static RAM GND 5164AZ8-2 PIN NAME Data inputs and outputs ...

Page 3

... Output deselect High-Z RATING UNIT -0.3 to +7 -30 to +60 C -65 to +150 C = - MIN. TYP. MAX. 3 -0.3 0.2 = - 3 LH5164AZ8 SUPPLY CURRENT NOTE Standby ( Standby ( Operating ( Operating ( Operating ( NOTE 1 1 UNIT ...

Page 4

... LH5164AZ8 AC CHARACTERISTICS (1) READ CYCLE (T = - PARAMETER Read cycle Address access time (CE ) Chip enable 1 access time ( Output enable access time Output hold time (CE ) Chip enable to 1 output in Low-Z ( Output enable to output in Low-Z (CE ) Chip enable to 1 output in High-Z ( Output disable to output in High-Z ...

Page 5

... CCDR 0 CCDR – 0 CCDR t CDR ACE1 t LZ1 t ACE2 t LZ2 OLZ DATA VALID Figure 3. Read Cycle LH5164AZ8 MIN. MAX. UNIT 2 HZ1 t HZ2 t OHZ t OH NOTE 5164AZ8-3 5 ...

Page 6

... LH5164AZ8 ADDRESS OUT D IN NOTES: 1. The writing occurs during an overlapping period defined as the time from the last occuring transit, either the time when the writing is finished defined as the time from address change to writing start. ...

Page 7

... (NOTE (NOTE 3) (NOTE (NOTE (NOTE 5) DATA VALID = "LOW," "HIGH," and WE = "LOW" LOW transit or CE HIGH transit Figure 5. OE Low Fixed LH5164AZ8 t (NOTE (NOTE 5164AZ8-5 7 ...

Page 8

... LH5164AZ8 CE CONTROL (NOTE 2 0 CCDR CONTROL 2 CCDR 0 NOTE: To control the data hold mode at CE during the data hold mode. 8 DATA HOLD MODE t CDR 0 CCDR DATA HOLD MODE t CDR CE 0 fix the input level of CE ...

Page 9

... TYP. 0.50 [0.020] 0.30 [0.012 18.20 [0.717] 17.80 [0.701] MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT ORDERING INFORMATION LH5164AZ8 Device Type Example: LH5164AZ8 (CMOS 64K ( Static RAM, 200 ns, 28-pin, 450-mil SOP) 1.70 [0.067] 15 8.80 [0.346] 12.40 [0.488] 8.40 [0.331] 11.60 [0.457] 14 1.70 [0.067] 0.15 [0.006] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] ...

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