m58wr032et STMicroelectronics, m58wr032et Datasheet
m58wr032et
Related parts for m58wr032et
m58wr032et Summary of contents
Page 1
... PROGRAM/ERASE CYCLES per BLOCK April 2004 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory Figure 1. Package ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Top Device Code, M58WR032ET: 8814h – Bottom Device Code, M58WR032EB: 8815h M58WR032ET M58WR032EB FBGA VFBGA56 (ZB) 7 1/81 ...
Page 2
... M58WR032ET, M58WR032EB TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. VFBGA Connections (Top view through package Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address Inputs (A0-A20 Data Input/Output (DQ0-DQ15 Chip Enable (E Output Enable (G Write Enable (W) ...
Page 3
... Program Status Bit (SR4 Status Bit (SR3 Program Suspend Status Bit (SR2 Block Protection Status Bit (SR1 Bank Write/Multiple Word Program Status Bit (SR0 Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CONFIGURATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Read Select Bit (CR15 X-Latency Bits (CR13-CR11 Wait Polarity Bit (CR10 M58WR032ET, M58WR032EB 3/81 ...
Page 4
... M58WR032ET, M58WR032EB Data Output Configuration Bit (CR9 Wait Configuration Bit (CR8 Burst Type Bit (CR7 Valid Clock Edge Bit (CR6 Wrap Burst Bit (CR3 Burst length Bits (CR2-CR0 Table 9. Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 10. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 6. X-Latency and Data Output Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 7 ...
Page 5
... Figure 20.VFBGA56 Daisy Chain - PCB Connection Proposal (Top view through package PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 26. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 27. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 APPENDIX A.BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 28. Top Boot Block Addresses, M58WR032ET Table 29. Bottom Boot Block Addresses, M58WR032EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 APPENDIX B.COMMON FLASH INTERFACE Table 30. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 31. CFI Query Identification String Table 32 ...
Page 6
... M58WR032ET, M58WR032EB Figure 29.Enhanced Factory Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Enhanced Factory Program Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 30.Quadruple Enhanced Factory Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Quadruple Enhanced Factory Program Pseudo Code APPENDIX D.COMMAND INTERFACE STATE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 40. Command Interface States - Modify Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 41. Command Interface States - Modify Table, Next Output . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 42 ...
Page 7
... Table memory maps are shown in Figure 4. eter Blocks are located at the top of the memory address space for the M58WR032ET, and at the bottom for the M58WR032EB. Each block can be erased separately. Erase can be suspended, in order to perform program in any other block, and then resumed. Program can be suspended to read data in any other block and then resumed ...
Page 8
... M58WR032ET, M58WR032EB Figure 2. Logic Diagram DDQ A0-A20 W E M58WR032ET G M58WR032EB SSQ 8/81 Table 1. Signal Names A0-A20 DQ0-DQ15 DQ0-DQ15 WAIT K L WAIT DDQ AI07303 SS V SSQ NC Address Inputs Data Input/Outputs, Command Inputs Chip Enable ...
Page 9
... A16 DQ12 DQ6 DQ4 DQ2 DQ13 DQ11 DQ10 DQ5 V DD DQ3 V DDQ Parameter Blocks 4 Mbits 8 blocks of 4 KWords 4 Mbits - 4 Mbits - 4 Mbits - 4 Mbits - 4 Mbits - M58WR032ET, M58WR032EB A18 A6 A4 A17 A5 A3 A19 DQ1 E A0 DQ9 DQ0 G DQ8 V SSQ AI07352 Main Blocks ...
Page 10
... M58WR032ET, M58WR032EB Figure 4. Memory Map M58WR032ET - Top Boot Block Address lines A20-A0 000000h 32 KWord 007FFFh Bank 7 038000h 32 KWord 03FFFFh 100000h 32 KWord 107FFFh Bank 3 138000h 32 KWord 13FFFFh 140000h 32 KWord 147FFFh Bank 2 178000h 32 KWord 17FFFFh 180000h 32 KWord 187FFFh Bank 1 1B8000h 32 KWord 1BFFFFh 1C0000h ...
Page 11
... V Ground. V SSQ the input/output circuitry driven by V must be connected to V RPH Voltages). Note: Each device in a system should have DDQ M58WR032ET, M58WR032EB . Clock Reset provides the power DD provides the power DDQ . V can be DD DDQ or can use a separate supply. ...
Page 12
... M58WR032ET, M58WR032EB ramic capacitor close to the pin (high frequen- cy, inherently low inductance capacitors should be as close as possible to the pack- age). See Figure 9., AC Measurement Load Cir- BUS OPERATIONS There are six standard bus operations that control the device. These are Bus Read, Bus Write, Ad- dress Latch, Output Disable, Standby and Reset ...
Page 13
... States - Modify and Lock Tables, for a summary of the Command Interface. The Command Interface is split into two types of commands: Standard commands and Factory Program commands. The following sections ex- plain in detail how to perform each command. M58WR032ET, M58WR032EB Table 4. Command Codes Hex Code 01h Block Lock Confirm 03h ...
Page 14
... M58WR032ET, M58WR032EB COMMAND INTERFACE - STANDARD COMMANDS The following commands are the basic commands used to read, write to and configure the device. Refer to Table 5., Standard Commands, in con- junction with the following text descriptions. Read Array Command The Read Array command returns the addressed bank to Read Array mode ...
Page 15
... C., Figure 21., Program Flow- chart and Pseudo Code, for the flowchart for using the Program command. M58WR032ET, M58WR032EB Program/Erase Suspend Command The Program/Erase Suspend command is used to pause a Program or Block Erase operation. A Bank Erase operation cannot be suspended. One bus write cycle is required to issue the Pro- gram/Erase command ...
Page 16
... M58WR032ET, M58WR032EB programming operation then read the array. See APPENDIX C., Figure 24., Program Suspend & Resume Flowchart and Pseudo Code, and 26., Erase Suspend & Resume Flowchart and Pseudo Code, for flowcharts for using the Pro- gram/Erase Resume command. Protection Register Program Command ...
Page 17
... QD=Query Data, BA=Block Address, BKA= Bank Address, PD=Program Data, PRA=Protection Register Address, PRD=Protection Register Data, CRD=Configuration Register Data. 2. Must be same bank as in the first cycle. The signature addresses are listed in 3. Any address within the bank can be used. M58WR032ET, M58WR032EB power-down. Table 13. ter issuing a Block Lock-Down command. Refer to ...
Page 18
... M58WR032ET, M58WR032EB Table 6. Electronic Signature Codes Manufacturer Code Top Device Code Bottom Locked Unlocked Block Protection Locked and Locked-Down Unlocked and Locked-Down Reserved Configuration Register ST Factory Default Security Block Permanently Locked Protection Register Lock OTP Area Permanently Locked Security Block and OTP Area Permanently ...
Page 19
... A0 and A1. Five bus write cycles are necessary to issue the Quadruple Word Program command. The first bus cycle sets up the Double Word Program Command. M58WR032ET, M58WR032EB Table 14., Pro- Table 14., Pro data IL C., Figure 22., Double Word Pro- ...
Page 20
... M58WR032ET, M58WR032EB The second bus cycle latches the Address and the Data of the first word to be written. The third bus cycle latches the Address and the Data of the second word to be written. The fourth bus cycle latches the Address and the Data of the third word to be written. ...
Page 21
... After the setup command is issued, read operations output the Status Register data. The Read Status Register command must not be issued as it will be interpreted as data to program. M58WR032ET, M58WR032EB Load Phase. The Load Phase requires 4 cycles to load the data (refer to Table 7., Factory Program Commands and Figure 30 ...
Page 22
... M58WR032ET, M58WR032EB If the Program and Verify Phase has successfully completed the memory returns to Read mode. If the P/E.C. fails to program and reprogram a given Table 7. Factory Program Commands Command Phase Add 2 BKA Bank Erase BKA or (4) 3 Double Word Program WA1 BKA or (5) 5 Quadruple Word Program ...
Page 23
... Erase Suspend Status Bit (SR6). The Suspend Status bit indicates that an Erase opera- tion has been suspended or is going to be sus- M58WR032ET, M58WR032EB pended in the addressed block. When the Erase Suspend Status bit is High (set to ‘1’), a Program/ Erase Suspend command has been issued and the memory is waiting for a Program/Erase Re- sume command ...
Page 24
... M58WR032ET, M58WR032EB or Erase operation. Indeterminate results can oc- cur if V becomes invalid during an operation. PP When the V Status bit is Low (set to ‘0’), the volt- PP age on the V pin was sampled at a valid voltage; PP when the V Status bit is High (set to ‘1’), the V PP ...
Page 25
... Error Bank Write Status Status SR0 Multiple Word Program Status (Enhanced Status Factory Program mode) Note: Logic level ’1’ is High, ’0’ is Low. M58WR032ET, M58WR032EB Logic Level ’1’ Ready ’0’ Busy ’1’ Erase Suspended ’0’ Erase In progress or Completed ’ ...
Page 26
... M58WR032ET, M58WR032EB CONFIGURATION REGISTER The Configuration Register is used to configure the type of bus access that the memory will per- form. Refer to Read Modes section for details on read operations. The Configuration Register is set through the Command Interface. After a Reset or Power-Up the device is configured for asynchronous page read (CR15 = 1) ...
Page 27
... Valid Clock Edge CR5-CR4 CR3 Wrap Burst CR2-CR0 Burst Length M58WR032ET, M58WR032EB serts the WAIT output to indicate that a delay is necessary before the data is output. If the starting address is aligned word boundary no wait states are needed and the WAIT output is not asserted. ...
Page 28
... M58WR032ET, M58WR032EB Table 10. Burst Type Definition Start 4 Words Address Sequential Interleaved 0 0-1-2-3 0-1-2-3 1 1-2-3-0 1-0-3-2 2 2-3-0-1 2-3-0-1 3 3-0-1-2 3-2-1-0 ... 7 7-4-5-6 7-6-5-4 ... Sequential Interleaved 0 0-1-2-3 1 1-2-3-4 2 2-3-4-5 3 3-4-5-6 ... 7 7-8-9-10 ... 60 60-61-62-63 61 61-62-63-WAIT-64 62-63-WAIT-WAIT- 62 64-65 63-WAIT-WAIT- 63 WAIT-64-65-66 28/81 8 Words Sequential Interleaved 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 Sequential Interleaved 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9... 3-4-5-6-7-8-9-10 7-8-9-10-11-12-13-14 60-61-62-63-64-65-66- 67 61-62-63-WAIT-64-65- 66-67-68 62-63-WAIT-WAIT-64- 65-66-67-68-69 63-WAIT-WAIT-WAIT- 64-65-66-67-68-69-70 Continuous Burst 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... 3-4-5-6-7-8-9... 7-8-9-10-11-12-13... 60-61-62-63-64-65-66... 61-62-63-WAIT-64-65-66... 62-63-WAIT-WAIT-64-65-66... 63-WAIT-WAIT-WAIT-64-65- 66... Same as for Wrap (Wrap /No Wrap ...
Page 29
... VALID ADDRESS DQ15-DQ0 WAIT CR8 = '0' CR10 = '0' WAIT CR8 = '1' CR10 = '0' WAIT CR8 = '0' CR10 = '1' WAIT CR8 = '1' CR10 = '1' X-latency 2nd cycle 3rd cycle 4th cycle tQVK_CPU tACC VALID DATA VALID DATA M58WR032ET, M58WR032EB tK tKQV tQVK_CPU VALID DATA VALID DATA AI08105 NOT VALID VALID DATA AI08106 29/81 ...
Page 30
... M58WR032ET, M58WR032EB READ MODES Read operations can be performed in two different ways depending on the settings in the Configura- tion Register. If the clock signal is ‘don’t care’ for the data output, the read operation is Asynchro- nous; if the data output is synchronized with clock, the read operation is Synchronous. ...
Page 31
... Signature Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes M58WR032ET, M58WR032EB Figure 13., Single Synchronous Read 12 show the dual operations possi- Program/ Program/ Block Erase Erase Erase Suspend Resume Yes Yes Yes Yes – ...
Page 32
... M58WR032ET, M58WR032EB BLOCK LOCKING The M58WR032E features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection. Lock/Unlock - this first level allows software- only control of block locking. Lock-Down - this second level requires hardware interaction before locking can be changed ...
Page 33
... Read Electronic Signature command with All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status transition locked block will restore the previous DQ0 value, giving a 111 or 110. IH M58WR032ET, M58WR032EB Next Protection Status (WP, DQ1, DQ0) After After ...
Page 34
... M58WR032ET, M58WR032EB PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES The Program and Erase times and the number of Program/ Erase cycles per block are shown in ble 14. In the M58WR032E the maximum number Table 14. Program, Erase Times and Program, Erase Endurance Cycles Parameter ...
Page 35
... Output Short Circuit Current O t Time for VPPH PP PPH M58WR032ET, M58WR032EB plied. Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Value Min Max – ...
Page 36
... Input Capacitance IN C Output Capacitance OUT Note: Sampled only, not 100% tested. 36/81 Conditions summarized in and AC Measurement should check that the operating conditions in their circuit match the operating conditions when rely- ing on the quoted parameters. M58WR032ET, M58WR032EB 70 80 Min Max Min Max 1.7 2.2 1.65 2.2 1.7 3 ...
Page 37
... I V Supply Current (Read) PP2 PP (1) V Supply Current (Standby PP3 Note: 1. Sampled only, not 100% tested Dual Operation current is the sum of read and program or erase currents. DD M58WR032ET, M58WR032EB Test Condition Min DDQ OUT DDQ ...
Page 38
... M58WR032ET, M58WR032EB Table 19. DC Characteristics - Voltages Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage Program Voltage-Logic PP1 Program Voltage Factory PPH PP V Program or Erase Lockout PPLK V V Lock Voltage LKO ...
Page 39
... Figure 10. Asynchronous Random Access Read AC Waveforms M58WR032ET, M58WR032EB 39/81 ...
Page 40
... M58WR032ET, M58WR032EB Figure 11. Asynchronous Page Read AC Waveforms 40/81 ...
Page 41
... Min 0 Max 17 Min 0 Max 17 Max 20 Min 0 Min 0 Max 17 Min 9 Min 10 Min 9 Min 9 Max 70 Min 0 after the falling edge of E without increasing t GLQV M58WR032ET, M58WR032EB = 1.65V-2. 2.2V-3.3V DDQ 80 100 70 80 100 80 100 70 80 100 80 100 70 80 100 ...
Page 42
... M58WR032ET, M58WR032EB Figure 12. Synchronous Burst Read AC Waveforms 42/81 ...
Page 43
... Figure 13. Single Synchronous Read AC Waveforms M58WR032ET, M58WR032EB 43/81 ...
Page 44
... M58WR032ET, M58WR032EB Figure 14. Clock input AC Waveform tKHKL Table 21. Synchronous Read AC Characteristics Symbol Alt t t Address Valid to Clock High AVKH AVCLKH t t Chip Enable Low to Clock High ELKH ELCLKH t Chip Enable Low to Wait Valid ELTV Chip Enable Pulse Width t EHEL (subsequent synchronous reads) ...
Page 45
... Figure 15. Write AC Waveforms, Write Enable Controlled M58WR032ET, M58WR032EB 45/81 ...
Page 46
... M58WR032ET, M58WR032EB Table 22. Write AC Characteristics, Write Enable Controlled Symbol Alt t t Address Valid to Next Address Valid AVAV WC t Address Valid to Latch Enable High AVLH (3) t Address Valid to Write Enable High t WC AVWH t t Data Valid to Write Enable High DVWH DS t Chip Enable Low to Latch Enable High ...
Page 47
... Figure 16. Write AC Waveforms, Chip Enable Controlled M58WR032ET, M58WR032EB 47/81 ...
Page 48
... M58WR032ET, M58WR032EB Table 23. Write AC Characteristics, Chip Enable Controlled Symbol Alt t t Address Valid to Next Address Valid AVAV Address Valid to Chip Enable High AVEH WC t Address Valid to Latch Enable High AVLH t t Data Valid to Write Enable High DVEH Chip Enable High to Address Transition ...
Page 49
... Supply Voltages High to Reset (3) t VDHPH High Note: 1. The device Reset is possible but not guaranteed Sampled only, not 100% tested important to assert RP in order to allow proper CPU initialization during Power-Up or Reset. M58WR032ET, M58WR032EB tPHWL tPHEL tPHGL tPHLL Reset Test Condition During Program ...
Page 50
... M58WR032ET, M58WR032EB PACKAGE MECHANICAL Figure 18. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Bottom View Package Outline BALL "A1" A Note: Drawing is not to scale. Table 25. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Package Mechanical Data millimeters Symbol Typ 0.660 b 0 ...
Page 51
... Figure 19. VFBGA56 Daisy Chain - Package Connections (Top view through package M58WR032ET, M58WR032EB AI07731 51/81 ...
Page 52
... M58WR032ET, M58WR032EB Figure 20. VFBGA56 Daisy Chain - PCB Connection Proposal (Top view through package START POINT 52/ END POINT AI07755 ...
Page 53
... T = Tape & Reel Packing Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. M58WR032ET, M58WR032EB M58WR032ET ...
Page 54
... M58WR032ET, M58WR032EB APPENDIX A. BLOCK ADDRESS TABLES Table 28. Top Boot Block Addresses, M58WR032ET Size Bank # Address Range (KWord 1FF000-1FFFFF 1 4 1FE000-1FEFFF 2 4 1FD000-1FDFFF 3 4 1FC000-1FCFFF 4 4 1FB000-1FBFFF 5 4 1FA000-1FAFFF 6 4 1F9000-1F9FFF 7 4 1F8000-1F8FFF 8 32 1F0000-1F7FFF 9 32 1E8000-1EFFFF 10 32 1E0000-1E7FFF 11 32 1D8000-1DFFFF ...
Page 55
... M58WR032ET, M58WR032EB 30 32 0B8000-0BFFFF 29 32 0B0000-0B7FFF 28 32 0A8000-0AFFFF 27 32 0A0000-0A7FFF 26 32 098000-09FFFF 25 32 090000-097FFF 24 32 088000-08FFFF 23 32 080000-087FFF 22 32 078000-07FFFF 21 32 ...
Page 56
... M58WR032ET, M58WR032EB APPENDIX B. COMMON FLASH INTERFACE The Common Flash Interface is a JEDEC ap- proved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory ...
Page 57
... Typical time-out for full chip erase = 2 23h 0003h Maximum time-out for word program = 2 24h 0004h Maximum time-out for quadruple word = 2 25h 0002h Maximum time-out per individual block erase = 2 26h 0000h Maximum time-out for chip erase = 2 M58WR032ET, M58WR032EB Description n µs n µ times typical n ...
Page 58
... M58WR032ET, M58WR032EB Table 33. Device Geometry Definition Offset Word Data Mode 27h 0016h Device Size = 2 28h 0001h Flash Device Interface Code description 29h 0000h 2Ah 0003h Maximum number of bytes in multi-byte program or page = 2 2Bh 0000h 2Ch 0002h Number of identical sized erase block regions within the device ...
Page 59
... Description bit field of optional features follows at the end of the bit-30 field. bit active(1 = Yes No) M58WR032ET, M58WR032EB Value "P" "R" "I" "1" "0" No Yes ...
Page 60
... Synchronous mode read capability configuration 2 (P+17)h = 50h 0007h Synchronous mode read capability configuration 3 Table 37. Bank and Erase Block Region Information M58WR032ET (top) M58WR032EB (bottom) Offset Data Offset (P+18)h =51h 02h (P+18)h =51h Note: 1. The variable pointer which is defined at CFI offset 15h. ...
Page 61
... M58WR032ET, M58WR032EB Description Data 01h Number of identical banks within Bank Region 1 00h Number of program or erase operations allowed in region 1: 11h Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks ...
Page 62
... Bank Regions. There are two Bank Regions, 1 contains all the banks that are made up of main blocks only, 2 contains the banks that are made up of the parameter and main blocks. Table 39. Bank and Erase Block Region 2 Information M58WR032ET (top) M58WR032EB (bottom) Offset ...
Page 63
... Note: 1. The variable pointer which is defined at CFI offset 15h. 2. Bank Regions. There are two Bank Regions, Region 1 contains all the banks that are made up of main blocks only, Region 2 con- tains the banks that are made up of the parameter and main blocks. M58WR032ET, M58WR032EB Description Data ...
Page 64
... M58WR032ET, M58WR032EB APPENDIX C. FLOWCHARTS AND PSEUDO CODES Figure 21. Program Flowchart and Pseudo Code Start Write 40h or 10h (3) Write Address & Data Read Status Register (3) NO SR7 = 1 YES Invalid SR3 = 0 Error (1, 2) YES NO SR4 = 0 Error (1, 2) YES NO Program to Protected SR1 = 0 Block Error (1, 2) ...
Page 65
... Error (1, 2) error_handler ( ) ; if (status_register.SR4==1) /*program error */ Program error_handler ( ) ; Error ( (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; } Invalid) and b4 (Program Error) can be made after each program operation or after PP M58WR032ET, M58WR032EB addressToProgram2, dataToProgram2) /*see note (4)*/ /*see note (3) */ /*see note (3) */ "see note (4)" AI06171b 65/81 ...
Page 66
... M58WR032ET, M58WR032EB Figure 23. Quadruple Word Program Flowchart and Pseudo Code Start Write 56h Write Address 1 & Data 1 (3, 4) Write Address 2 & Data 2 (3) Write Address 3 & Data 3 (3) Write Address 4 & Data 4 (3) Read Status Register (4) NO SR7 = 1 YES Invalid ...
Page 67
... SR7 = 1 YES NO SR2 = 1 YES Write FFh Read data from another address Write D0h Program Continues M58WR032ET, M58WR032EB program_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (bank_address, 0x70 read status register to check if program has already completed */ do { status_register=readFlash (bank_address must be toggled*/ } while (status_register.SR7 Program Complete if (status_register.SR2==0) /*program completed */ { writeToFlash (bank_address, 0xFF) ...
Page 68
... M58WR032ET, M58WR032EB Figure 25. Block Erase Flowchart and Pseudo Code Start Write 20h (2) Write Block Address & D0h Read Status Register (2) NO SR7 = 1 YES NO SR3 = 0 YES YES SR4, SR5 = 1 Sequence Error ( SR5 = 0 YES NO Erase to Protected SR1 = 0 YES End Note error is found, the Status Register must be cleared before further Program/Erase operations. ...
Page 69
... YES Write FFh Read data from another block or Program/Protection Program or Block Protect/Unprotect/Lock Write D0h Erase Continues M58WR032ET, M58WR032EB erase_suspend_command ( ) { writeToFlash (bank_address, 0xB0) ; writeToFlash (bank_address, 0x70 read status register to check if erase has already completed */ do { status_register=readFlash (bank_address must be toggled*/ } while (status_register.SR7 (status_register.SR6==0) /*erase completed */ Erase Complete { writeToFlash (bank_address, 0xFF) ...
Page 70
... M58WR032ET, M58WR032EB Figure 27. Locking Operations Flowchart and Pseudo Code Start Write 60h (1) Write 01h, D0h or 2Fh Write 90h (1) Read Block Lock States NO Locking change confirmed? YES Write FFh (1) End Note: 1. Any address within the bank can equally be used. 70/81 locking_operation_command (address, lock_operation) { writeToFlash (address, 0x60) ...
Page 71
... Error (1, 2) error_handler ( ) ; Program if (status_register.SR4==1) /*program error */ Error (1, 2) error_handler ( ) ; if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; } Invalid) and SR4 (Program Error) can be made after each program operation or PP M58WR032ET, M58WR032EB /*see note ( see note (3) */ AI06177b 71/81 ...
Page 72
... M58WR032ET, M58WR032EB Figure 29. Enhanced Factory Program Flowchart SETUP PHASE Write 30h Address WA1 Write D0h Address WA1 Read Status Register NO SR7 = 0? Check SR4, SR3 YES and SR1 for program, V and Lock Errors PP SR0 = 0? Exit YES Write PD1 PROGRAM PHASE Address WA1 ...
Page 73
... Exit Phase */ /* status register polling */ do{ status_register=readFlash(any_address must be toggled */ } while (status_register.b7==0); if (status_register.b4==1) /*program failure error*/ error_handler(); if (status_register.b3==1) /*VPP invalid error*/ error_handler(); if (status_register.b1==1) /*program to protect block error*/ error_handler(); } } M58WR032ET, M58WR032EB status_register=readFlash(any_address must be toggled*/ status_register=readFlash(any_address must be toggled*/ 73/81 ...
Page 74
... M58WR032ET, M58WR032EB Figure 30. Quadruple Enhanced Factory Program Flowchart SETUP PHASE Start Write 75h Address WA1 FIRST LOAD PHASE Write PD1 Address WA1 Read Status Register NO SR7 = 0? YES Check SR4, SR3 and SR1 for program, PROGRAM AND V and Lock Errors PP VERIFY PHASE Exit Note: 1 ...
Page 75
... must be toggled */ } while (status_register.SR7==0); if (status_register.SR1==1) /*program to protected block error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR4==1) /*program failure error*/ error_handler(); } } /*EFP aborted for an error*/ if (status_register.SR4==1) /*program error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR1==1) /*program to protect block er- error_handler(); M58WR032ET, M58WR032EB 75/81 ...
Page 76
... M58WR032ET, M58WR032EB APPENDIX D. COMMAND INTERFACE STATE TABLES Table 40. Command Interface States - Modify Table, Next State Program Program WP Current CI State Read setup (2) Array (3,4) Program Ready Ready Setup Lock/CR Setup Setup OTP Busy Setup Busy Program Suspend Setup Busy Erase Program in Erase Suspend ...
Page 77
... EFP Block Setup Erase Setup Unlock Setup confirm, (3,4) EFP Confirm Status Register Status Register Status Register Output Unchanged Status Register Output Unchanged M58WR032ET, M58WR032EB Read Program/ Read Electronic Clear status Erase Status signature, Register Suspend Register Read CFI (5) Query Status Output ...
Page 78
... M58WR032ET, M58WR032EB Table 42. Command Interface States - Lock Table, Next State Current CI State Lock/CR OTP Setup (4) Setup Lock/CR Ready OTP Setup Setup Lock/CR Setup Ready (Lock error) Setup OTP Busy Setup Program Busy Suspend Setup Busy Lock/CR Erase Setup in Suspend Erase Suspend ...
Page 79
... Illegal commands are those not defined in the command set. Next Output State After Command Input Block Block Lock Set CR Lock-Down Confirm Confirm (3) Confirm Status Register Status Register Array Output Unchanged Output Unchanged M58WR032ET, M58WR032EB EFP Exit, P/E. C. Illegal Quad EFP Operation Command (2) Completed (4) Exit Output Unchanged Output Status Register ...
Page 80
... M58WR032ET, M58WR032EB REVISION HISTORY Table 44. Document Revision History Date Version 07-Aug-2002 1.0 First Issue Clear Status Register Configuration Register Command 5, 7 clarified; 12-Dec-2002 1.1 Synchronous Read WAIT Active Low bar removed from Figures 10, 11. Note 4 added to Figure modified in Figure 13. Package mechanical information corrected and Daisy Chain added (Figures 20) ...
Page 81
... All other names are the property of their respective owners. Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States © 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES www.st.com M58WR032ET, M58WR032EB 81/81 ...