tc58dvm92a3ta00 TOSHIBA Semiconductor CORPORATION, tc58dvm92a3ta00 Datasheet - Page 15

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tc58dvm92a3ta00

Manufacturer Part Number
tc58dvm92a3ta00
Description
512-mbit 64 M ? 8 Bits Cmos Nand E Prom
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TC58DVM92A3TA00
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information.
Command Latch Enable: CLE
register. The command is latched into the command register from the I/O port on the rising edge of the WE
signal while CLE is High.
Address Latch Enable: ALE
address/data register. Address information is latched on the rising edge of WE if ALE is High. Input data is
latched if ALE is Low.
Chip Enable:
ignored when device is in Busy state (
will not enter Standby mode even if the CE input goes High.
Write Enable:
Read Enable:
I/O Port: I/O1 to 8
the device.
Write Protect:
regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.
Ready/Busy:
Busy state (
(
pulled-up to Vcc with an appropriate resister.
RY
The CLE input signal is used to control loading of the operation mode command into the internal command
The ALE signal is used to control loading of either address information or input data into the internal
The device goes into a low-power Standby mode when CE goes High during a wait state. The CE signal is
The WE signal is used to control the acquisition of data from the I/O port.
The RE signal controls serial data output. Data is available t
The internal column address counter is also incremented (Address = Address + l) on this falling edge.
The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from
The WP signal is used to protect the device from accidental programming or erasing. The internal voltage
The
/
BY
RY
= H) after completion of the operation. The output buffer for this signal is an open drain and has to be
/
BY
RY
/
RY/
CE
output signal is used to indicate the operating condition of the device. The
BY
WE
WP
RE
= L) during the Program, Erase and Read operations and will return to Ready state
BY
RY
/
BY
= L), such as during a Program or Erase or Read operation, and
15
REA
after the falling edge of RE .
TC58DVM92A3TA00
RY
/
BY
2008-12-10
signal is in

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