tc58dvm92a1fti0

Manufacturer Part Numbertc58dvm92a1fti0
Description512-mbit 64m U 8 Bits Cmos Nand E2 Prom
ManufacturerTOSHIBA Semiconductor CORPORATION
tc58dvm92a1fti0 datasheet
 


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TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
512-MBIT (64M u 8 BITS) CMOS NAND E
DESCRIPTION
The device is a single 3.3 V 512-Mbit (553,648,128) bit NAND Electrically Erasable and Programmable Read-Only
2
Memory (NAND E
PROM) organized as 528 bytes u 32 pages u 4096 blocks. The device has a 528-byte static register
which allows program and read data to be transferred between the register and the memory cell array in 528-byte
increments. The Erase operation is implemented in a single block unit (16 Kbytes  512 bytes: 528 bytes u 32 pages).
The device is a serial-type memory device which utilizes the I/O pins for both address and data input/output as
well as for command inputs. The Erase and Program operations are automatically executed making the device most
suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and
other systems which require high-density non-volatile memory data storage.
FEATURES
x Organization
Memory cell allay 528 u 128K u 8
Register
528 u 8
Page size
528 bytes
Block size
(16K  512) bytes
x Modes
Read, Reset, Auto Page Program,
Auto Block Erase, Status Read,
Multi Block Program, Multi Block Erase
x Mode control
Serial input/output
Command control
PIN ASSIGNMENT
(TOP VIEW)
NC
1
NC
2
NC
3
NC
4
NC
5
GND
6
7
RY
/
BY
RE
8
CE
9
NC
10
NC
11
V
12
CC
V
13
SS
NC
14
NC
15
CLE
16
ALE
17
WE
18
WP
19
NC
20
NC
21
22
NC
NC
23
NC
24
x TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide
for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
x The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer’s own risk.
x The products described in this document are subject to the foreign exchange and foreign trade laws.
x The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
x The information contained herein is subject to change without notice.
2
PROM
x Power supply
x Program/Erase Cycles 1E5 cycle (with ECC)
x Access time
Cell array to register 25 Ps max
Serial Read Cycle
x Operating current
Read (50 ns cycle)
Program (avg.)
Erase (avg.)
Standby
x Package
TSOPI48-P-1220-0.50 (Weight: 0.53g typ.)
PIN NAMES
48
NC
I/O1 to I/O8
I/O port
47
NC
46
NC
CE
Chip enable
45
NC
44
I/O8
WE
Write enable
43
I/O7
42
I/O6
RE
Read enable
41
I/O5
40
NC
CLE
Command latch enable
39
NC
ALE
Address latch enable
38
NC
37
V
CC
WP
Write protect
36
V
SS
35
NC
RY
/
BY
Ready/Busy
34
NC
33
NC
GND
Ground input
32
I/O4
31
I/O3
V
Power supply
30
I/O2
CC
29
I/O1
V
Ground
28
NC
SS
27
NC
26
NC
25
NC
TC58DVM92A1FTI0
V
2.7 V to 3.6 V
CC
50 ns min
10 mA typ.
10 mA typ.
10 mA typ.
50 PA max.
000707EBA1
2003-07-11 1/44

tc58dvm92a1fti0 Summary of contents

  • Page 1

    ... Address latch enable Write protect Ready/Busy GND Ground input 32 I/O4 31 I/O3 V Power supply 30 I/ I/O1 V Ground TC58DVM92A1FTI0 min 10 mA typ typ typ max. 000707EBA1 2003-07-11 1/44 ...

  • Page 2

    ... This parameter is periodically sampled and is not tested for every device. * Status register Address register Command register Control HV generator  0 MHz) CONDITION OUT TC58DVM92A1FTI0 Column buffer Column decoder Data register Sense amp Memory cell array VALUE UNIT  0 0 ...

  • Page 3

    ... OUT cycle cycle cycle cycle   0V 400 2 pin V 0 TC58DVM92A1FTI0 TYP. MAX UNIT 4096 Blocks  TYP. MAX UNIT 3 0.8 V MIN TYP. MAX UNIT ...

  • Page 4

    ... CE High to Ready (When interrupted Read Mode) CRY t Device Reset Time (Read/Program/Erase) RST AC TEST CONDITIONS PARAMETER Input level Input pulse rise and fall time Input comparison level Output data comparison level Output load TC58DVM92A1FTI0 MIN MAX UNIT NOTES ...

  • Page 5

    ... If the delay CEH signal stays Ready 100 ns CEH 527 A Busy t CRY MIN TYP. 200  2  200     2 TC58DVM92A1FTI0 pin Busy signal is not output. MAX UNIT NOTES 1000 1000 (1) ...

  • Page 6

    ... TIMING DIAGRAMS Latch Timing Diagram for Command/Address/Data CLE ALE I/O1 to I/O8 Command Input Cycle Timing Diagram CLE t CLS ALS ALE t DS I/O1 to I/O8 Setup Time Hold Time CLH ALH t DH TC58DVM92A1FTI0 : 2003-07-11 6/44 ...

  • Page 7

    ... A16 A17 to A24 TC58DVM92A1FTI0 ALH A25 : CLH ...

  • Page 8

    ... BY * 70H represents the hexadecimal number REH RHZ REA RHZ t CLS WHC CSTO t WHR TC58DVM92A1FTI0 CHZ REA RHZ t CEA t CHZ RSTO RHZ Status output : 2003-07-11 8/44 ...

  • Page 9

    ... A24 ALH AR2 REA A17 D D OUT A25 to A24 TC58DVM92A1FTI0 t CEH t CRY OUT OUT OUT 527 CHZ RC t RHZ OUT OUT ...

  • Page 10

    ... Read operation using 50H command ALH A17 A25 to A16 to A24 t ALH A17 A25 to A16 to A24 TC58DVM92A1FTI0 t AR2 REA OUT OUT OUT 256  N 256  527 : AR2 ...

  • Page 11

    ... A24 Page t R address M Page M access A17 A25 to A24 Page t R 256  256  256  address Page M access TC58DVM92A1FTI0 527 527 t R Page access : 527 527 t R Page access : ...

  • Page 12

    ... Sequential Read (3) Timing Diagram CLE CE WE ALE RE A9 I/O1 A0 50H I/O8 A16 Column address A17 A25 to A24 Page t R 512  512  512  address Page M access TC58DVM92A1FTI0 527 512 513 514 527 t R Page access : 2003-07-11 12/44 ...

  • Page 13

    ... Do not input data while data is being output ALH WB BERASE D0H Erase Start Busy command : not input data while data is being output TC58DVM92A1FTI0 t PROG 10H 70H Status output 70H Status output Status Read command ...

  • Page 14

    ... A16 (Page programming in multi block) t ALH t ALS A17 A25 527 IN Auto program (dummy) Max 3 times repeat 31 times repeat Max 4 blocks programming TC58DVM92A1FTI0 t DBSY 11H 80H to A7 Last district input 2 2003-07-11 14/44 ...

  • Page 15

    ... Do not input data while data is being output. times repeat 2 (Page programming in multi block) t ALH t ALS A17 A25 527 IN Auto program (multi block program) Last district input 31 times repeat Max 4 blocks programming TC58DVM92A1FTI0 t MBPBSY 15H 80H Max 3 times repeat 2003-07-11 15/44 ...

  • Page 16

    ... Do not input data while data is being output. 3 (Last pages programming in multi block) t ALH t ALS A17 A25 527 IN Auto program (dummy) Max 3 times repeat Max 4 blocks programming TC58DVM92A1FTI0 t DBSY 11H 80H Last district input 2003-07-11 16/44 ...

  • Page 17

    ... Do not input data while data is being output. 4 Max 3 times repeat (Last pages programming in multi block) t ALH t ALS A17 A25 527 IN Auto program (true) Last district input Max 4 blocks programming TC58DVM92A1FTI0 t PROG 10H 71H Status output 5 Status read 2003-07-11 17/44 ...

  • Page 18

    ... A9 to A17 to 60H A16 A24 to I/O8 Auto Block Erase Setup command Max 4 times repeat : not input data while data is being output ALH WB BERASE D0H A25 Erase Start Busy command TC58DVM92A1FTI0 71H Status output Status Read command 2003-07-11 18/44 ...

  • Page 19

    ... ALH ALS ALE I/O1 91H to I/ CEA t t ALH ALEA t REAID t REAID 00 98H Address Maker code input CEA t t ALH ALEA t REAID 00 20H Address input TC58DVM92A1FTI0 76H Device code : 2003-07-11 19/44 ...

  • Page 20

    ... The Busy state ( during the Program, Erase and Read operations and will return to Ready state ( after completion of the operation. The output buffer for this signal is an open drain. TC58DVM92A1FTI0 ...

  • Page 21

    ... A25 CLE ALE TC58DVM92A1FTI0 (16K  512) bytes Column address A9 to A25 : Page address A14 to A25 : Block address A9 to A13 : NAND address in block 0V/Vcc 2003-07-11 21/44 ...

  • Page 22

    ... Second Cycle Acceptable while Busy     ?     TC58DVM92A1FTI0 HEX data bit assignment (Example) Serial Data Input: 80H I/ I/O1 I/O1 to I/O8 Power Output Active High impedance Active High impedance Standby 2003-07-11 22/44 ...

  • Page 23

    ... The operation of the device after input of the 01H command is the same as that of Read mode (1). If the start pointer set after column address 256, use Read mode (2). However, for a Sequential Read, output of the next page starts Cell array from column address 0. TC58DVM92A1FTI0 2003-07-11 23/44 ...

  • Page 24

    ... A4-to-A7 address. (A “00H” command is necessary to move the pointer back to the 0-to-511 main memory cell location.) Data output Busy Busy (01H) 256 527 A Sequential Read (2) TC58DVM92A1FTI0 Data output t R Busy (50H) 512 527 A Sequential Read (3) 2003-07-11 24/44 ...

  • Page 25

    ... Fail: 1 Busy: 0 Not Protected Device 3 Busy 70H Status on Device N BY pin signals from multiple devices are wired together as shown in the TC58DVM92A1FTI0 The Pass/Fail status on I/O1 is only valid when the device is in the Ready state Device Device ...

  • Page 26

    ... Verify operations Block Address Erase Start input: 3 cycles command TC58DVM92A1FTI0 70 Status Read command automatically returns to Ready after completion of the operation. The data is transferred (programmed) from the register to the selected page on the rising edge of WE following input of the “10H” command. ...

  • Page 27

    ... Dummy Dummy Data input Program Program command command command Data input Address Data input 0 to 527 input 0 to 527 (District 1) (District 2) TC58DVM92A1FTI0 Multi block Data input Program command command 80 15 Address Data input input 0 to 527 80 15 (District 3) 2003-07-11 27/44 ...

  • Page 28

    ... I/O2 describes Pass/Fail condition. If Pass: 0 Fail: 1 more than one fail occurred in 32 times (512  16 byte) page write operation in Pass: 0 Fail: 1 District 0 area, it shows “Fail” condition. Do not care I/O3, I/O4 and I/O5 are as same manner Ready: 1 Busy I/O2. Protect: 0 Not Protect: 1 TC58DVM92A1FTI0 2003-07-11 28/44 ...

  • Page 29

    ... Untill the Ready condition after the programming terminated by “10H” command, effective bit in the Status data is limited on Ready/Busy bit. In other words, Pass/Fail condition can be checked only in the Ready condition after “10H” command. TC58DVM92A1FTI0 ···.., Block 4092 ···.., Block 4093 · ...

  • Page 30

    ... If at least one fail occurred in Max 4 Blocks Pass: 0 Fail: 1 erase operation, it shows “Fail” condition. Pass: 0 Fail: 1 I/O2 describes Pass/Fail condition. Pass: 0 Fail fail occurred in District 0 area, it shows “Fail” condition. Pass: 0 Fail not care I/O3, I/O4 and I/O5 are as same manner as I/O2. Ready: 1 Busy: 0 Protect: 0 Not Protect: 1 TC58DVM92A1FTI0 2003-07-11 30/44 ...

  • Page 31

    ... Example 1 : (60) [District 2] (60) [District 0] (60) [District 1] (D0) Example 2 : (60) [District 0] (60) [District 1] (60) [District 2] (60) [District 3] (D0) It requires no mutual address relation between the selected blocks from each District. TC58DVM92A1FTI0 ···.., Block 4092 ···.., Block 4093 ···.., Block 4094 · ...

  • Page 32

    ... The second FF t (max RST FF t RST FF t (max RST command is invalid, but the third TC58DVM92A1FTI0 Figure 8. 00 Figure 9. 00 (max 500 P s) Figure 10. 00 Figure 11. I/O status: Pass/Fail o Pass Ready/Busy o Ready I/O status: Ready/Busy o Busy Figure 12. (2) ( command is valid ...

  • Page 33

    ... Table 6. ID Codes read out by ID read command (1) 90H I/O8 I/O7 Maker code 1 0 Device code CEA t ALEA t REAID 98H Maker code , t and t refer to the AC Characteristics. REAID CEA ALEA Figure 13. ID Read timing I/O6 I/O5 I/O4 I/O3 I/ TC58DVM92A1FTI0 76H Device code I/O1 Hex Data 0 98H 0 76H 2003-07-11 33/44 ...

  • Page 34

    ... Address 00 For the specifications of the access times t Table 7. ID Codes read out by command 91H I/O8 I/O7 Extended ID code CEA t ALEA t REAID 20H Extended ID code , t and t refer to the AC Characteristics. REAID CEA ALEA Figure 14. ID Read timing I/O6 I/O5 I/O4 I/O3 I/ TC58DVM92A1FTI0 I/O1 Hex Data 0 20H 2003-07-11 34/44 ...

  • Page 35

    ... V and CE signal is kept high Operation Figure 15. Power-on/off Sequence becomes 2 recommends starting access after about CC FF Reset Figure 16. For this operation the “FFH” command is needed. TC58DVM92A1FTI0 Don’t care V IL 2003-07-11 35/44 ...

  • Page 36

    ... Read mode. In this case, data output starts automatically from address N and address input is unnecessary Ex.) Random page program (Prohibition) DATA IN: Data (1) Page 0 Page 1 Page 2 Page 15 Page 31 Figure 17. page programming within a block 70 Status Read command input Figure 18. TC58DVM92A1FTI0 Data (32) Data register (2) (16) (3) (1) (32) 00 [A] Status Read Status output 2003-07-11 36/44 ...

  • Page 37

    ... C area Add Start point A area 10H Add DIN Start point C Area 10H Add DIN Start point B Area Figure 20. Example of How to Set the Pointer TC58DVM92A1FTI0 255 256 511 512 527 B C Pointer control 50H Add Start point C area 00H Add Start point ...

  • Page 38

    ... We recommend that you use this data as a reference when selecting a resistor value Ready 1.0 V Busy TC58DVM92A1FTI0 / BY buffer consists of an open drain 3 25° 100 ...

  • Page 39

    ... The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE DIN (100 ns min) WW Disable Programming WE DIN (100 ns min) WW Enable Erasing WE 60 DIN (100 ns min) WW Disable Erasing WE DIN (100 ns min) WW TC58DVM92A1FTI0 2003-07-11 39/44 ...

  • Page 40

    ... Although the device may read in a fifth address ignored inside the chip. Read operation CLE CE WE ALE I/O 00H, 01H or 50H Program operation CLE CE WE ALE I/O 80H Address input WE Internal read operation starts when WE goes High in the fourth cycle. Figure 22. Address input ignored Figure 23. TC58DVM92A1FTI0 ignored Data input 2003-07-11 40/44 ...

  • Page 41

    ... Busy state. (Refer to Figure 25.) I/O 00H/01H/50H Hence the RE clock input must start after the address input. All 1s Data Pattern 2 All 1s All 1s Data Pattern 2 Figure 24. Address input Figure 25. TC58DVM92A1FTI0 Data Pattern 3 Data Pattern 3 2003-07-11 41/44 ...

  • Page 42

    ... MIN Valid (Good) Block Number 4016 Read Check: to verify the column address of Start Block No 1 Fail Read Check Pass Bad Block * 1 Block No. 4096 Yes End Figure 27 TC58DVM92A1FTI0 TYP. MAX UNIT 4096 Block  517bytes of the first page in the block with FF (Hex) 2003-07-11 42/44 ...

  • Page 43

    ... Block Verify after Program o Retry (2) ECC When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an external buffer. Then, Block A prevent further system accesses to Block A (by creating a bad block table or by using an another appropriate scheme). Block B Figure 28. TC58DVM92A1FTI0 2003-07-11 43/44 ...

  • Page 44

    ... Package Dimensions TC58DVM92A1FTI0 2003-07-11 44/44 ...