tc58dvm92a1fti0 TOSHIBA Semiconductor CORPORATION, tc58dvm92a1fti0 Datasheet - Page 24

• Manufacturer Part Number: tc58dvm92a1fti0
• Description: 512-mbit 64m U 8 Bits Cmos Nand E2 Prom
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RY
CLE
ALE
Read Mode (3)
16-byte redundancy area of the page. The start pointer is therefore set to a value between byte 512 and byte 527.
/
Sequential Read (1) (2) (3)
Read mode (3) outputs the contents of the redundant address locations only.
needed.
WE
CE
RE
BY
I/O
Read mode (3) has the same timing as Read modes (1) and (2) but is used to access information in the extra
This mode allows the sequential reading of pages without additional address input.
Sequential Read modes (1) and (2) output the contents of addresses 0 to 527 as shown above, while Sequential
When the page address reaches the next block address, read command (00H/01H/50H) and address inputs are
RY
00H
01H
50H
/
BY
50H
(00H)
Figure 5. Read mode (3) operation
0
Sequential Read (1)
Address input
A
512
A0 to
527
A3
Busy
t
R
527
(01H)
Sequential Read (2)
Data output
256
Busy
A
redundant memory cells, while A4 to A7 are ignored.
Once a “50H” command has been issued, the pointer moves to
the redundant cell locations and only those 16 cells can be
addressed, regardless of the value of the A4-to-A7 address.
the 0-to-511 main memory cell location.)
Addresses bits A0 to A3 are used to set the start pointer for the
(A “00H” command is necessary to move the pointer back to
527
Busy
t
R
Data output
(50H)
Sequential Read (3)
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512 527
A
Busy
t
R