tc58dvm92a1fti0 TOSHIBA Semiconductor CORPORATION, tc58dvm92a1fti0 Datasheet - Page 36

• Manufacturer Part Number: tc58dvm92a1fti0
• Description: 512-mbit 64m U 8 Bits Cmos Nand E2 Prom
• Manufacturer: TOSHIBA Semiconductor CORPORATION

command
(6)
(7)
RY
/
WE
CE
BY
RE
Addressing for program operation
the block to MSB (most significant bit) page of the block. Random page address programming is prohibited.
Status Read during a Read operation
mode.
to Read mode. In this case, data output starts automatically from address N and address input is unnecessary
From the LSB page to MSB page
DATA IN: Data (1)
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of
The device status can be read out by inputting the Status Read command “70H” in Read mode.
Once the device has been set to Status Read mode by a “70H” command, the device will not return to Read
Therefore, a Status Read during a Read operation is prohibited.
However, when the Read command “00H” is input during [A], Status mode is reset and the device returns
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Page 0
Page 1
Page 2
00
Address N
Data (32)
Data register
(16)
(32)
(1)
(2)
(3)
Figure 17. page programming within a block
Figure 18.
Ex.) Random page program (Prohibition)
DATA IN: Data (1)
command input
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Status Read
Page 0
Page 1
Page 2
70
Data (32)
Status Read
Data register
TC58DVM92A1FTI0
(16)
(32)
(2)
(3)
(1)
[A]
00
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Status output