tc58dvm92a1fti0 TOSHIBA Semiconductor CORPORATION, tc58dvm92a1fti0 Datasheet - Page 41

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tc58dvm92a1fti0

Manufacturer Part Number
tc58dvm92a1fti0
Description
512-mbit 64m U 8 Bits Cmos Nand E2 Prom
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
(12)
(13)
RY
/
WE
RE
BY
I/O
Several programming cycles on the same page (Partial Page Program)
Note regarding the RE signal
Therefore, once the device has been set to Read mode by a “00H”, “01H” or “50H” command, the internal
column address counter is incremented by the RE clock independently of the address input timing, If the
internal read operation (array to register) will occur and the device will enter Busy state. (Refer to Figure 25.)
RE clock input pulses start before the address input, and the pointer reaches the last column address, an
2nd programming
3rd programming
1st programming
A page can be divided into up to 3 segments. Each segment can be programmed individually as follows:
Hence the RE clock input must start after the address input.
RE The internal column address counter is incremented synchronously with the RE clock in Read mode.
00H/01H/50H
Result
Note: The input data for unprogrammed or previously programmed page segments must be “1”
(i.e. the inputs for all page bytes outside the segment which is to be programmed should be set to all “1”).
Data Pattern 1
Data Pattern 1
All 1s
Data Pattern 2
Data Pattern 2
All 1s
Figure 24.
Figure 25.
All 1s
Address input
All 1s
TC58DVM92A1FTI0
Data Pattern 3
Data Pattern 3
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