tc58dvm72f1ft00 TOSHIBA Semiconductor CORPORATION, tc58dvm72f1ft00 Datasheet
tc58dvm72f1ft00
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tc58dvm72f1ft00 Summary of contents
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... TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. xThe information contained herein is subject to change without notice. TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2 PROM and 1 ...
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... PIN ASSIGNMENT (TOP VIEW) TC58DVM72F1FT00 / TC58DAM72F1FT00 TC58DVM72A1FT00 / TC58DAM72A1FT00 x16 GND GND CLE CLE 16 ALE ALE 17 WE ...
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... T Operating Temperature opr CAPACITANCE *(Ta =25° MHz) SYMB0L PARAMETER C Input IN C Output OUT This parameter is periodically sampled and is not tested for every device. * TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Status register Address register Command register Control HV generator VALUE TC58DVxxxxx 0.6~4.6 0.6~4.6 0.6~4 ½ 4 0.6 V~V 0.6 V~V CCQ 0 ...
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... CCO8 I Standby Current CCS1 I Standby Current CCS2 V High Level Output Voltage OH V Low Level Output Voltage Output Current TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 MIN 1004 MIN 2.7 2.7 2.0 0.3 * MIN 2.7 1. 0.78 CCQ 0 CONDITION CCQ ...
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... CE High to Ready(When interrupted Read Mode) CRY t Device Reset Time (Read/Program/Erase) RST AC TEST CONDITIONS PARAMETER Input level Input pulse rise and fall time Input comparison level Output data comparison level Output load TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 MIN MAX ...
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... PARAMETER t Programming Time PROG Number of Programming Cycles on Same N Page t Block Erasing Time BERASE (1): Refer to Application Note (12) toward the end of this document. TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 is greater than or equal to 100 ns. If the delay CEH signal stays Ready 100 ns CEH A 527 A ...
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... Latch Timing Diagram for Command/Address/Data CLE ALE I/O1 to I/O8 Command Input Cycle Timing Diagram CLE t CLS ALS ALE t DS I/O1 to I/O8 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Setup Time Hold Time CLH ALH 2003-01-24 7/34 ...
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... Address Input Cycle Timing Diagram t CLS CLE ALS ALE I/O1 to I/O8 Data Input Cycle Timing Diagram CLE ALS ALE WE I/O1 to I/O8 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 A16 ...
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... Status Read Cycle Timing Diagram CLE t t CLS CLH I/O1 70H * to I/ 70H represents the hexadecimal number TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 REH RHZ REA RHZ t CLS WHC CSTO ...
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... ALH ALS ALE I/O1 00H I/O8 Column address Read Operation using 00H Command 255 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 t t ALH AR2 REA D OUT A9 to A16 A17toA23 ...
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... CLH ALH ALS ALE I/O1 50H to I/O8 Column address Read Operation using 50H Command N: 0 to15 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 t t ALH A16 A17toA23 ALH ...
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... Page address address Sequential Read (2) Timing Diagram CLE CE WE ALE RE I/O1 01H A16 A17toA23 to I/O8 Column Page address address TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Page M access t R 256 256 Page M access 527 527 t R ...
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... Sequential Read (3) Timing Diagram CLE CE WE ALE RE I/O1 50H A16 A17toA23 to I/O8 Column Page address address TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 t R 512 512 512 Page M access 527 512 513 527 t R Page access : 2003-01-24 13/34 ...
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... CLS ALS ALH ALE I/O1 60H A9 to A16 A17toA23 to I/O8 Auto Block Erase Setup command TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 t ALH t ALS 527 : not input data while data is being output ...
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... ID Read Operation Timing Diagram CLE t CLS t CLS ALH ALS ALE I/O1 90H to I/O8 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 CEA t ALH t ALEA t REAID t REAID 00 98H Address Maker code input 73H Device code : 2003-01-24 15/34 ...
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... The Busy state ( during the Program, Erase and Read operations and will return to Ready state ( after completion of the operation. The output buffer for this signal is an open drain. TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 ...
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... A23 * : A8 is automatically set to Low or High by a 00H command or a 01H command. I/O9-16 should be low when address is input. * I/O8 must be set to Low in the third cycle. TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 I/O1 A page consists of 528 bytes in which 512 bytes are used I/O8 for main memory storage and 16 bytes are for redundancy or for other uses ...
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... Table 4 shows the operation states for Read mode. Table 4. Read mode operation states CLE Output Select L Output Deselect TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 CLE ALE ...
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... Start-address input 256 M Select page N Figure 4. Read mode (2) operation TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Busy m A data transfer operation from the cell array to the register starts on the rising edge the third cycle (after the address information has been latched). The device will be in Busy state during this transfer period ...
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... When the pointer reaches the last address, the device continues to output the data from this address ** on each RE clock signal m=527,n=512 X16 : m=263,n=256 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Busy Addresses bits A0~A3 are used to set the start pointer for the redundant memory cells, while A4~A7 are ignored ...
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... I/O 70H Figure 6. Status Read timing application example System Design Note: If the RY diagram, the Status Read function can be used to determine the status of each individual device. TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 OUTPUT Fail: 1 Busy: 0 Not Protected Device 2 3 Busy ...
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... Verify operations Block Address Erase Start input: 2 cycles command TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 10 Status Read command completion of the operation. The data is transferred (programmed) from the register to the selected page on the rising edge of WE following input of the “10H” command. ...
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... When a Status Read command (70H) is input after a Reset When two or more Reset commands are input in succession The second TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 FF t (max RST FF t RST FF t (max RST command is invalid, but the third Figure 8 ...
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... Address 00 For the specifications of the access times t Table 6. ID Codes read out by ID read command 90H I/O8 I/O7 Maker code 1 0 Device code I/O9 to I/O16 are “0” . TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 t CEA t ALEA t REAID 98H Maker code , t and t refer to the AC Characteristics. REAID ...
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... If a command other than “10H” or “FFH” is input, the Program operation is not performed Command other than Programming cannot be executed. “10H” or “FFH” TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 reaches 2.5 V and CE signal is kept high Operation Figure 15. Power-on/off Sequence becomes 2 ...
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... Therefore, a Status Read during a Read operation is prohibited. However, when the Read command “00H” is input during [A], Status mode is reset and the device returns to Read mode. In this case, data output starts automatically from address N and address input is unnecessary TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Ex.) Random page program (Prohibition) ...
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... Add Start point C area 01H Add Start point B area To program region C only, set the start point to region C using the 50H command. 50H 80H 01H 80H TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Pointer 0 A (x16) 0~255 µµµ (1) 00H 256~263 (2) 01H (3) 50H Figure 19 Pointer control ...
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... A pull-up resistor needs to be used for termination because the circuit. V CCQ Device V SS Figure 21. This data may vary from device to device. We recommend that you use this data as a reference when selecting a resistor value. TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 DIN Ready V CCQ ...
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... The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE DIN (100 ns min) WW Disable Programming WE DIN (100 ns min) WW Enable Erasing WE DIN (100 ns min) WW Disable Erasing WE DIN (100 ns min) WW TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 29/34 ...
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... Although the device may read in a fourth address ignored inside the chip. Read operation CLE CE WE ALE I/O 00H, 01H, 50H Internal read operation starts when WE goes High in the third cycle. Program operation CLE CE WE ALE I/O 80H TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Address input Figure 22. Address input Ignored Figure 23. Ignored Data input 2003-01-24 30/34 ...
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... A page can be divided into segments. Each segment can be programmed individually as follows: 1st programming Data Pattern 1 2nd programming All 1s 3rd programming Result Data Pattern 1 Note: The input data for unprogrammed or previously programmed page segments must be “1” TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 All 1s Data Pattern 2 All 1s All 1s Data Pattern 2 Figure 24. Data Pattern 3 ...
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... Block No. Block No erase operation is allowed to detected bad blocks ç TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 At the time of shipment, all data bytes in a Valid Block are FFh(x8) or FFFFh(x16). For Bad Block, all bytes are not in the FFh state(x8) or FFFFh state(x16). Please don’t perform erase operation to Bad Block. ...
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... Do not turn off the power before write/erase operation is complete. Avoid using the device when the battery is low. Power shoetage and/or power failure before write/erase operation is complete will cause loss of data and/or damage to data. TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 DETECTION AND COUNTERMEASURE SEQUENCE ...
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... Package Dimensions Weight: 0.53g (typ.) TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Unit : mm 2003-01-24 34/34 ...