tc58dvm92a5baj3 TOSHIBA Semiconductor CORPORATION, tc58dvm92a5baj3 Datasheet - Page 15

• Manufacturer Part Number: tc58dvm92a5baj3
• Description: 512-mbit 64m ? 8 Bits Cmos Nand E Prom Description
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Schematic Cell Layout and Address Assignment
131072 pages
4096 blocks
Table 1. Addressing
First cycle
Second cycle
Third cycle
Fourth cycle
* : A8 is automatically set to Low or High by a 00h command or a 01h command.
The Program operation works on page units while the Erase operation works on block units.
l/O2-8 must be set to Low in the fourth cycle.
Figure 1. Schematic Cell Layout
512
528
I/O8
A16
A24
A7
* L
16
I/O7
A15
A23
A6
* L
I/O6
A14
A22
8I/O
A5
* L
I/O8
32 pages
1 block
I/O5
A13
A21
A4
* L
I/O1
I/O4
A12
A20
A3
* L
15
used for main memory storage and 16 bytes are for
redundancy or for other uses.
I/O3
A11
A19
A2
* L
A page consists of 528 bytes in which 512 bytes are
1 page = 528 bytes
1 block = 528 bytes × 32 pages = (16K + 512) bytes
Capacity = 528 bytes × 32 pages × 4096 blocks
An address is read in via the I/O port over four
consecutive clock cycles, as shown in Table 1.
I/O2
A10
A18
A1
* L
I/O1
A17
A25
A0
A9
A0 to A7: Column address
A9 to A25: Page address
A14 to A25: Block address
A9 to A13: NAND address in block
TC58DVM92A5BAJ3
2010-06-16