tc58dvm92a5baj3 TOSHIBA Semiconductor CORPORATION, tc58dvm92a5baj3 Datasheet - Page 21

• Manufacturer Part Number: tc58dvm92a5baj3
• Description: 512-mbit 64m ? 8 Bits Cmos Nand E Prom Description
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Auto Page Program
Auto Block Erase
after the address and data have been input. The sequence of command, address and data input is shown below.
(Refer to the detailed timing chart.)
follows the Erase Setup command “60h”. This two-cycle process for Erase operations acts as an ertra layer of
protection from accidental erasure of data due to external noise. The device automatically executes the Erase
and Verify operations.
The device carries out an Automatic Page Program operation when it receives a “10h” Program command
The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command “D0h” which
Data input
command
RY
RY
Data input
/
/
80
BY
BY
Selected
Figure 6. Auto Page Program operation
page
Address
60
Program
input
Block Address
input: 3 cycles
Data input
0 to 527
Erase Start
Reading & verification
command
command
Program
D0
10
page on the rising edge of WE following input of the “10h” command.
After programming, the programmed data is transferred back to the
register to be automatically verified by the device. If the programming
does not succeed, the Program/Verify operation is repeated by the
device until success is achieved or until the maximum loop number set in
the device is reached.
The data is transferred (programmed) from the register to the selected
Busy
21
completion of the operation.
RY
Status Read
Status Read
command
command
/
BY
70
70
automatically returns to Ready after
TC58DVM92A5BAJ3
I/O
I/O
Fail
Fail
Pass
Pass
2010-06-16