tc58dvm92a5baj3 TOSHIBA Semiconductor CORPORATION, tc58dvm92a5baj3 Datasheet - Page 30

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tc58dvm92a5baj3

Manufacturer Part Number
tc58dvm92a5baj3
Description
512-mbit 64m ? 8 Bits Cmos Nand E Prom Description
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

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I/O
Several programming cycles on the same page (Partial Page Program)
Note regarding the RE signal
mode. Therefore, once the device has been set to Read mode by a “00h”, “01h” or “50h” command, the
internal column address counter is incremented by the RE clock independently of the address input timing,
If the RE clock input pulses start before the address input, and the pointer reaches the last column
address, an internal read operation (array to register) will occur and the device will enter Busy state. (Refer
to Figure 23.)
2nd programming
A page can be divided into up to 3 segments. Each segment can be programmed individually as follows:
3rd programming
Hence the RE clock input must start after the address input.
1st programming
RE The internal column address counter is incremented synchronously with the RE clock in Read
00h/01h/50h
Result
Note: The input data for unprogrammed or previously programmed page segments must be “1”
Data Pattern 1
Data Pattern 1
All 1 s
Data Pattern 2
Data Pattern 2
All 1 s
30
Figure 23.
Figure 22
All 1 s
Address input
All 1 s
TC58DVM92A5BAJ3
Data Pattern 3
Data Pattern 3
2010-06-16

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