viper100bsp STMicroelectronics, viper100bsp Datasheet - Page 13

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viper100bsp

Manufacturer Part Number
viper100bsp
Description
Smps Primary I.c.
Manufacturer
STMicroelectronics
Datasheet

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placed into a standby mode with reduced
consumption and also provided to the external
capacitor connected to the V
the voltage on this pin reaches the high voltage
threshold V
turns into active mode and starts switching. The
start up current generator is switched off, and the
converter should normally provide the needed
current on the V
winding of the transformer, as shown on figure
15.
In case of abnormal condition where the auxiliary
winding is unable to provide the low voltage
supply current to the V
the output of the converter), the external
capacitor discharges itself down to the low
threshold voltage V
the device get back to the inactive state where
the internal circuits are in standby mode and the
start up current source is activated. The converter
enters a endless start up cycle, with a start-up
duty cycle defined by the ratio of charging current
towards discharging when the VIPer100B/BSP
tries to start. This ratio is fixed by design to 2 to
15, which gives a 12% start up duty cycle while
the power dissipation at start up is approximately
0.6 W, for a 230 Vrms input voltage. This low
value of start-up duty cycle prevents the stress of
the output rectifiers and of the transformer when
Figure 15: Behaviour of the high voltage current source at start-up
VDDoff
VDDon
VDD
DDon
of the UVLO logic, the device
DD
DDoff
pin through the auxiliary
DD
of the UVLO logic, and
pin (i.e. short circuit on
t
DD
Auxiliary primary
pin. As soon as
winding
15 mA
C
2 mA
VDD
VDD
VIP er100B
Sta rt up duty cycle ~ 10%
in short circuit.
The external capacitor C
be sized according to the time needed by the
converter to start up, when the device starts
switching. This time t
parameters, among which transformer design,
output
compensation network implemented on the
COMP pin. The following formula can be used for
defining the minimum capacitor needed:
C
where:
I
when switching. Refer to specified I
values.
t
device begins to switch. Worst case is generally
at full load.
V
logic. Refer to the minimum specified value.
Soft start feature can be implemented on the
COMP pin through a simple capacitor which will
be also used as the compensation network. In
this case, the regulation loop bandwidth is rather
low, because of the large value of this capacitor.
In case a large regulation loop bandwidth is
mandatory, the schematics of figure 16 can be
DD
SS
1 mA
DDhyst
VDD
UNDERVOLTAGE
LOCK OUT LOGIC
Ref.
is the start up time of the converter when the
is the consumption current on the V
15 mA
V
I
is the voltage hysteresis of the UVLO
DD
capacitors,
DDhyst
t
SS
3 mA
soft
VDD
SS
depends on many
start
on the V
VIPER100B/BSP
DRAIN
SOURCE
FC00100B
feature
DD1
DD
pin must
and I
DD
13/20
and
DD2
pin

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