100331QCX Fairchild Semiconductor, 100331QCX Datasheet

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100331QCX

Manufacturer Part Number
100331QCX
Description
IC FLIP FLOP LP TRPL D 28-PLCC
Manufacturer
Fairchild Semiconductor
Type
D-Type Busr
Datasheet

Specifications of 100331QCX

Function
Master Reset
Output Type
Differential
Number Of Elements
3
Number Of Bits Per Element
1
Frequency - Clock
400MHz
Delay Time - Propagation
1ns
Trigger Type
Positive Edge
Voltage - Supply
4.2 V ~ 5.7 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output High, Low
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
100331QCX
Manufacturer:
Fairchild Semiconductor
Quantity:
10 000
© 2000 Fairchild Semiconductor Corporation
100331SC
100331PC
100331QC
100331QI
100331
Low Power Triple D-Type Flip-Flop
General Description
The 100331 contains three D-type, edge-triggered master/
slave flip-flops with true and complement outputs, a Com-
mon Clock (CP
(MR) inputs. Each flip-flop has individual Clock (CP
Direct Set (SD
a master when both CP
to a slave when CP
Set, Master Reset and individual CD
ride the Clock inputs. All inputs have 50 k
resistors.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Order Number
CP
CP
D
CD
SD
MR
MS
Q
Q
0
0
0
–D
Pin Names
-Q
–Q
0
C
n
0
–CP
–CD
2
2
2
2
2
n
C
) and Direct Clear (CD
), and Master Set (MS) and Master Reset
Package Number
n
Individual Clock Inputs
Common Clock Input
Data Inputs
Individual Direct Clear Inputs
Individual Direct Set Inputs
Master Reset Input
Master Set Input
Data Outputs
Complementary Data Outputs
or CP
n
M24B
N24E
V28A
V28A
and CP
C
(or both) go HIGH. The Master
Description
C
are LOW and transfers
n
n
and SD
) inputs. Data enters
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range ( 40 C to 85 C)
n
inputs over-
DS010262
pull-down
n
),
Features
Connection Diagrams
35% power reduction of the 100131
2000V ESD protection
Pin/function compatible with 100131
Voltage compensated operating range
Available to industrial grade temperature range
Package Description
24-Pin DIP/SOIC
28-Pin PLCC
February 1990
Revised August 2000
www.fairchildsemi.com
4.2V to 5.7V

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100331QCX Summary of contents

Page 1

... MS Master Set Input Q -Q Data Outputs –Q Complementary Data Outputs 0 2 © 2000 Fairchild Semiconductor Corporation Features 35% power reduction of the 100131 2000V ESD protection Pin/function compatible with 100131 ), n Voltage compensated operating range Available to industrial grade temperature range inputs over- n pull-down Package Description ...

Page 2

Truth Tables Synchronous Operation (Each Flip-Flop) Inputs ...

Page 3

Absolute Maximum Ratings Storage Temperature (T ) STG Maximum Junction Temperature ( Pin Potential to Ground Pin ( Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 2) Commercial Version DC Electrical Characteristics 4.2V to ...

Page 4

Commercial Version (Continued) DIP AC Electrical Characteristics 4.2V to 5.7V GND EE CC CCA T Symbol Parameter Min f Toggle Frequency 375 MAX t Propagation Delay PLH 0. Output PHL C t Propagation Delay ...

Page 5

Commercial Version (Continued) Symbol Parameter Min t Propagation Delay PLH 0. Output PHL C t Propagation Delay PLH 0. Output PHL n t Propagation Delay PLH 0. Output PHL ...

Page 6

Industrial Version PLCC DC Electrical Characteristics 4.2V to 5.7V GND CCA Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL V Output HIGH Voltage OHC V Output LOW Voltage OLC V ...

Page 7

Test Circuits Notes 2V, V 2.5V CC CCA EE L1 and L2 Equal length 50 impedance lines R 50 terminator internal to scope T Decoupling 0.1 F from GND to V and All unused ...

Page 8

Switching Waveforms FIGURE 3. Propagation Delay (Clock) and Transition Times FIGURE 4. Propagation Delay (Resets) FIGURE 5. Data Setup and Hold Time Note the minimum time before the transition of the clock that information must be present at ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number M24B Package Number N24E 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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