x9530 Intersil Corporation, x9530 Datasheet
x9530
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x9530 Summary of contents
Page 1
... I1 TSSOP 14L 1 November 11, 2005 DESCRIPTION The X9530 is a highly integrated laser diode bias controller which incorporates two digitally controlled Programmable Current compensation with dedicated look-up tables, and supplementary EEPROM array. All functions of the device are controlled via a 2-wire digital serial interface. ...
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... The contents of the selected LUT row (8-bit wide) drives the input of an 8-bit D/A converter, which generated is generates the output current. connected All control and setup parameters of the X9530, including the look-up tables, are programmable via the 2-wire serial port ...
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... Current Generator 2 Output. This pin sinks or sources current. The magnitude and direction of the current is fully programmable and adaptive. The resolution is 8 bits. 3 X9530 The EEPROM array is internally organized as 272 x 8 bits with 16-Byte pages, and utilizes Intersil’s proprietary Direct Write™ cells, providing a minimum endurance of 100,000 Page Write cycles and a minimum data retention of 100 years ...
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... The I1DS bit sets the polarity of Current Generator 1, DAC1. When this bit is set to “0” (default), the Current GPM, LUT1, LUT2 Generator 1 of the X9530 is configured as a Current Source. Current Generator 1 is configured as a Current Sink when the I1DS bit is set to “1”. See Figure 5 ...
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... WEL Reserved Volatile Write Enable Latch 0: Write Disabled 1: Write Enabled ADC Output 87h AD5 AD4 Volatile Registers in byte addresses 88h through 8Fh are reserved. 5 X9530 NV1234 ADCfiltOff ADCIN VRM Control ADC ADC Input Voltage filtering Internal Reference ...
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... The I2DS bit sets the polarity of Current Generator 2, DAC2. When this bit is set to “0” (default), the Current Generator 2 of the X9530 is configured as a Current Source. Current Generator 2 is configured as a Current Sink when the I2DS bit is set to “1”. See Figure 5 ...
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... The WEL bit is enabled by writing ELECT IT ON 10000000 WEL bit remains set to “1” until the X9530 is powered down, and then up again, or until it is reset to “0” by writing 00000000 A Write operation that modifies the value of the WEL bit will not cause a change in other bits of Control ...
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... On-chip Voltage A/D Converter Input Select Reference The input signal to the A/D converter on the X9530, may be the output of the on-chip temperature sensor external source via the VSense pin. Bit ADCIN in Control register 0 selects between the two options (See Figure 4). It’s default value is “0”, which selects the internal temperature sensor ...
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... All voltages referred to Vss. 9 X9530 LOOK-UP TABLES The X9530 memory array contains two 64-byte look-up tables. One is associated to pin I1’s output current generator and the other to pin I2’s output current generator, through their corresponding D/A converters. The output of each look-up table is the byte contained in To A/D the selected row ...
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... Divider DAC2 Input byte or I2FSO[1:0] bits 1 and and 2 in Control Figure 6. Look-up Table (LUT) Operation LUT2 Row Selection bits D0h LUT1 Row Selection bits 90h 10 X9530 Vcc Polarity I1DS or I2DS: bits Control Select register 0. Circuit + - I1FSO[1: register 5 ...
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... The full scale output current has a maximum value of ±1.6 mA, which is obtained using a resistance of 510Ω for Rx. This resistance may be connected externally to pin Rx of the X9530, or may be selected from one of three internal values. Bits I1FSO1 and I1FSO0 select the full scale output current setting for I1 as described in “ ...
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... See Figure 5, and the descriptions of the control bits. 12 X9530 POWER-ON RESET When power is applied to the Vcc pin of the X9530, the device undergoes a strict sequence of events before the current outputs of the D/A converters are enabled. When the voltage at Vcc becomes larger than the power-on reset threshold voltage (V recalls all control bits from non-volatile memory into volatile registers ...
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... Data states on the SDA line can change only while SCL is LOW. SDA state changes while SCL is HIGH are reserved for indicating START and STOP conditions. See Figure 10. On power-up of the X9530, the SDA pin is in the input mode. Serial Start Condition ...
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... SDA Figure 10. Valid Data Changes on the SDA Bus SCL SDA Figure 11. Acknowledge Response From Receiver SCL from Master SDA Output from Transmitter SDA Output from Receiver START 14 X9530 START Data Stable Data Change 1 STOP Data Stable 8 9 ACK November 11, 2005 FN8211.1 ...
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... Write operation to any other bit. (See “WEL: Write Enable Latch (Volatile)” on page 7.) Also, all communication to the X9530 over the 2-wire serial bus is conducted by sending the MSB of each byte of data first. Even though the 2176 bit memory consists of four ...
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... ACK. The master then terminates the transfer by generating a STOP condition. At this time, if all data bits are volatile, the X9530 is ready for the next read or write operation. If some bits are nonvolatile, the X9530 begins the internal write cycle to the nonvolatile memory ...
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... Figure 16). After the receipt of each byte, the X9530 responds with an ACK, and the internal byte address counter is incremented by one. The page address remains constant. When the counter reaches the end of the page, it “ ...
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... START, the Slave Address byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Slave Address byte with the R/W bit set to “1”. After each of the three bytes, the X9530 responds with an ACK. Then the X9530 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eigth bit of each byte ...
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... WEL bit in Control 6 register; 2- The Block Lock can prevent Writes to certain regions of memory; 3- The Write Protection pin disables any writing to the X9530; 4- The proper clock count, data bit sequence, and STOP condition is required in order to start a nonvolatile write cycle, otherwise the X9530 ignores the Write operation ...
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... The surface mount package (TSSOP) and the Chip Scale Package both allow good thermal conduction from the PC board to the die, so the X9530 will provide an accurate measure of the temperature of the board. If there is no ambient air movement over the device package or the board, then the measured temperature will be very close to that of the board ...
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... Figure 20. Typical Laser Driver Circuit Topology High Speed Data Input I MODSET I BIASSET I PINSET Figure 21. X9530 Application Example Block Diagram High Speed Data Input X9530 INTERSIL XDCP MOD_DEF SDA (0) MOD_DEF SCK (1) 21 X9530 Laser Diode Driver Circuit Modulation Currrent Generation I I BIASMAX BIAS Σ ...
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... OHSDA V WP, A0, A1, and A2 input ILCMOS Low voltage 22 X9530 COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied ...
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... For this range of V(VRef) the full scale sink mode current at I1 and I2 follows V(VRef) with a linearity error smaller than 1%. 4. These parameters are periodically sampled and not 100% tested. 5. TCO = [Max V Min V(V ref REF 23 X9530 (CONTINUED) Min Typ Max 0.8 x Vcc Vcc 1 ...
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... The Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjust- DAC ing the measured transfer curve for Offset and Full Scale Error expressed in LSB. 3. These parameters are periodically sampled and not 100% tested. 24 X9530 Min Typ 1.56 1.58 ...
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... DNL errors starting from code 00h to the code where the INL measurement is desired. The measured trans- fer curve is adjusted for Offset and Fullscale errors before calculating INL. 3. These parameters are periodically sampled and not 100% tested. 25 X9530 510Ω, 0.1%, resistor connected between R1 and Vss, and another between R2 and Vss Min ...
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... STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 3. The minimum frequency requirement applies between a START and a STOP condition. 4. These parameters are periodically sampled and not 100% tested. 26 X9530 Min Typ Max (3) 1 ...
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... Figure 22. Bus Timing t F SCL t SU:DAT t SU:STA t HD:STA SDA IN SDA OUT Figure 23. WP Pin Timing START SCL SDA IN WP Figure 24. Non-Volatile Write Cycle Timing SCL SDA 8th bit of last byte 27 X9530 HIGH LOW R t HD:DAT Clk SU:WP HD:WP ACK Stop Condition t SU:STO ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 28 X9530 14-Lead Plastic, TSSOP, Package Code V14 .025 (.65) BSC .169 (4.3) ...