tza3015hw NXP Semiconductors, tza3015hw Datasheet

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tza3015hw

Manufacturer Part Number
tza3015hw
Description
30 Mbit/s To 3.2 Gbit/s A-rate 4-bit Fibre Optic Transceiver
Manufacturer
NXP Semiconductors
Datasheet

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Preliminary specification
Supersedes data of 2003 Oct 06
DATA SHEET
TZA3015HW
30 Mbit/s to 3.2 Gbit/s A-rate
4-bit fibre optic transceiver
INTEGRATED CIRCUITS
2003 Dec 16

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tza3015hw Summary of contents

Page 1

... DATA SHEET TZA3015HW 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver Preliminary specification Supersedes data of 2003 Oct 06 INTEGRATED CIRCUITS 2003 Dec 16 ...

Page 2

... Adjustable swing for CML serial data and clock outputs Programmable polarity of RF I/Os Clock versus data swap for optimum connectivity Swap of parallel bus for optimum connectivity Mute function for a forced logic 0 output state Programmable parity Programmable 32-bit frame detection. 2 Preliminary specification TZA3015HW ...

Page 3

... NAME TZA3015HW HTQFP100 2003 Dec 16 GENERAL DESCRIPTION The TZA3015HW is a fully integrated optical network transceiver containing a limiter, data and clock recovery circuit, clock synthesizer demultiplexer and multiplexer. The A-rate feature allows the IC to operate at any bit rate between 30 Mbit/s and 3.2 Gbit/s with one single reference frequency ...

Page 4

... LPF TZA3015HW FREQUENCY WINDOW DETECTOR CLEAN-UP PLL 98 (1) ( CCD IPUMP INWINDOW WINSIZE RXPRSCL/ RXPRSCLQ Fig.1 Block diagram. 4 Preliminary specification TZA3015HW TXPCO/ TXPARERR/ TXPCOQ ENDDR TXPARERRQ 79 86, 87 PHASE SHIFT 64 65 CLK 88 ÷ 4 MUX PARITY CHECK 74 AND ...

Page 5

... CCD TXPC TXPCQ V CCD TXPD0 TXPD0Q TXPD1 TXPD1Q TXPD2 TXPD2Q TXPD3 TXPD3Q 5 Preliminary specification TZA3015HW PIN DESCRIPTION 36 supply voltage (digital part) 37 wide and narrow frequency detect window select input 38 frequency window detector output 39 supply voltage (digital part) 40 ground 41 enable low LVDS swing ...

Page 6

... TXPRSCL TXPRSCLQ LOL V CCA CREF CREFQ FREF1 IPUMP V CCD RXPRSCL RXPRSCLQ Preliminary specification TZA3015HW PIN DESCRIPTION 89 prescaler synthesizer output 90 prescaler synthesizer output inverted 91 loss of lock output 92 supply voltage (analog part) 93 reference clock input 94 reference clock input inverted 95 reference frequency select ...

Page 7

... RXSD RXSDQ 17 V CCA 18 LOSTH 19 RSSI 20 LOS 21 CS(DR0) 22 SDA(DR1) 23 SCL(DR2 2003 Dec 16 TZA3015HW Fig.2 Pin configuration. 7 Preliminary specification TZA3015HW V CCD 75 74 TXPD3Q 73 TXPD3 TXPD2Q 72 71 TXPD2 70 TXPD1Q TXPD1 69 TXPD0Q 68 67 TXPD0 66 V CCD TXPCQ 65 64 TXPC V CCD ...

Page 8

... C-bus registers, regardless of the user interface. See Table 21 for the defaults and a detailed list of all I registers and the meaning of their contents. 2003 Dec 16 Some functions of the TZA3015HW can be controlled both using pre-program mode and via the I cases, an extra I 2 C-bus mode or ...

Page 9

... Fibre Channel 2125.00 Receiver L IMITING AMPLIFIER The TZA3015HW contains a limiting amplifier (see Fig.3). To achieve optimum receiver sensitivity for any bit rate, the bandwidth of the amplifier is automatically scaled with the bit rate. Wideband noise of the optical front-end (photo detector and transimpedance amplifier) is thus reduced for lower bit rates ...

Page 10

... Loss Of Signal (LOS) indicator Besides the analog RSSI output, a digital LOS indication is present on the TZA3015HW. The RSSI level is internally compared with a LOS threshold, which can be set by connecting an external resistor to pin LOSTH or by means of an internal DAC which is accessible via the I ...

Page 11

... Any crystal-based oscillator that generates a reasonably accurate frequency (e.g. 100 ppm) will do. This only holds if the TZA3015HW is used as a receiver since the synthesizer of the transmitter uses the same reference clock. The transmitter does need a very accurate reference frequency ...

Page 12

... Fig.7 and Tables 4 and 5. Figure 7 shows the position of the most commonly used line rates in relation to the defined octaves of the TZA3015HW. Table 5 lists the most commonly used standards together with the associated line rates. Table 4 clarifies the octave definitions ...

Page 13

... Write K j into registers C3h, C4h, C5h or E3h, E4h, E5h Convert N to binary and write into registers C1h, C2h or E1h, E2h END MCE413 Fig.8 Flowchart for calculating N and K. 13 Preliminary specification TZA3015HW no yes no k 0.75 ? yes 0 0 ...

Page 14

... MHz (see Table 3). 2003 Dec 128 bit rate M R 2666.05714283 Mbits = --------------------------------------- - = ---------------------------------------------------------------------------- - f 38.88 MHz ref 2 1 109.3106996 = n = 218. Consequently the appropriate values are (register 146.9268293 = 293. Consequently the appropriate values are (register 14 Preliminary specification TZA3015HW 1 2 137.1428571 = ...

Page 15

... RXPRSCLINV of register DDR&RXPRSCL (D5h). 288 to 336 If no prescaler information is desired, the output can be 576 to 672 disabled by bit RXPRSCLEN of the same register. Apart 15 Preliminary specification TZA3015HW ) is single-ended, the unused CREF ref source power supply will be attenuated ref 1 C ---------------------------------- - ...

Page 16

... RXFP(Q). Any header pattern can be programmed through registers HEADER3 to HEADER0 (B0h to B3h possible to enter a ‘don’t care’ for any bit position, e.g. to program a header pattern that is much shorter than 32 bits or to program a pattern with a gap in it. 16 Preliminary specification TZA3015HW ...

Page 17

... Fig.12). Byte boundary detection is disabled on the first RXFP pulse after ENBA has gone LOW. Figure 13 shows frame and byte boundary detection activated on the rising edge of ENBA and deactivated by the first RXFP pulse after ENBA has gone LOW. 17 Preliminary specification TZA3015HW LSB HEADER bit ...

Page 18

... With bit RXPARINV of register RXMFOUTC0 (D4h), the parity can be made odd parity check is required, bit RXPAREN of register RXMFOUTC0 (D4h) can be programmed to disable this output, to reduce power dissipation. 18 Preliminary specification TZA3015HW A2, bits 0-3 valid ...

Page 19

... PHASE CHARGE PUMP FREQUENCY AND down DETECTOR LOOP FILTER MAIN DIVIDER N, K ÷ N Fig.14 Schematic diagram of the clock synthesizer. 19 Preliminary specification TZA3015HW OCTAVE DIVIDER VCO to LM MUX ÷ M and multiplexer MGU682 ...

Page 20

... Tables 4 and 5 and Fig.7. Figure 7 shows the position of the most commonly used line rates in relation to the defined octaves of the TZA3015HW. Table 5 clarifies the octave definitions; this yields the value for the octave divider M. The value for R is determined by the reference frequency and the received bit rate (see Section “ ...

Page 21

... TXPD0Q to TXPD3Q TXPC TX_CLK TXPCQ TXPCO TX_CLK_SRC TXPCOQ FIFORESET CREF Fig.15 Co-directional clocking diagram. FRAMER TXPAR TX_PARITY TXPARQ 4 TXPD0 to TXPD3 TX_DATA 4 TXPD0Q to TXPD3Q TXPCO TX_CLK_SRC TXPCOQ FIFORESET CREF Fig.16 Contra-directional clocking diagram. 21 Preliminary specification TZA3015HW TZA3015HW system clock TZA3015HW system clock ...

Page 22

... Bit TXBUSSWAP of register MUXCON1 (F0h) swaps the bus order of the parallel data input bus TXPD0(Q) to TXPD3(Q). Bit TXBUSSWAP reverses the order of bits from MSB to LSB, or vice versa, to allow for optimum MODE connectivity on the PCB. 22 Preliminary specification TZA3015HW MODE 1 TXPCO in DDR mode 0 TXPCO in normal mode 2 C-bus control of ...

Page 23

... If the reference divider R is used, this requirement elevates with approximately 20 log R. Configuring the main functionality O PERATING MODES The TZA3015HW can be configured in several operating modes. It can be configured as: Transceiver Transmitter Receiver Transponder with clean-up PLL. The transceiver configuration is the default operating mode ...

Page 24

... SYNTHESIZER data DCR DEMULTIPLEXER clock Fig.17 Line loop back mode. data 4 MULTIPLEXER clock SYNTHESIZER data DCR DEMULTIPLEXER clock Fig.18 Diagnostic loop back mode. 24 Preliminary specification TZA3015HW 4 4 parallel data parallel clock parallel 4 4 data parallel clock MCE416 4 4 parallel data ...

Page 25

... R and C1 is mandatory and will transform the current at the output of the charge pump into a control voltage for the VXCO. Capacitor C2 is optional. The internal clock and data path in the TZA3015HW is clarified in Fig.21. As can be seen in the clean-up application, the received (and transmitted) data is also available in parallel format at the parallel output bus ...

Page 26

... Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver handbook, full pagewidth from PHASE DCR FREQUENCY DETECTOR bit: CLUPPLLINV Fig.20 Clean-up PLL application with the TZA3015HW. handbook, full pagewidth serial data serial clock serial data LIMITER I/O configuration LVDS OUTPUTS Several options exist that allow flexible configuration of the LVDS outputs: output amplitude, signal polarity, bus order, mute and selective enable/disable of various outputs ...

Page 27

... The serial RF outputs are CML type outputs (see Figs 31 and 32). Several options exist that allow flexible configuration of the RF outputs: output amplitude adjustment, signal polarity, data-clock swap, output termination and selective enable/disable of the clock output. Thus, the TZA3015HW can be configured so that 27 Preliminary specification TZA3015HW and ...

Page 28

... TXSDSCSWAP of register TXRFOUTC1 (F3h). Allowing full flexibility in the PCB design. The data and clock outputs can be DC- or AC-coupled to the laser driver. The TZA3015HW serial RF outputs can be adapted to this for optimal connectivity by appropriately setting bit RFOUTTERMAC of register TXRFOUTC0 (F4h). DC termination is default. ...

Page 29

... O - PEN DRAIN OUTPUT The TZA3015HW contains one open-drain interrupt output pin INT. The output type of the interrupt controller can be configured by programming bit INTOUT of register INTCONF (A5h). The output can be configured as a push-pull CMOS output open-drain output. For the open-drain configuration an external pull-up resistor of 3 ...

Page 30

... In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition. Fig.22 Start and stop conditions START condition Fig.23 (Not) acknowledge condition on the I 30 Preliminary specification TZA3015HW SDA SCL P STOP condition MBC622 not acknowledge acknowledge 8 9 clock pulse for acknowledgement ...

Page 31

... After the start command (S) the receiver sends the address of the slave device, waits for an acknowledge from the transmitter slave, receives data from the slave (slave, TZA3015HW, starts sending data after generating the acknowledge), after receiving the data, the receiver (master) sends an acknowledge finished a not-acknowledge followed by a stop condition (P) ...

Page 32

... Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver 2 I C-BUS REGISTERS The TZA3015HW can be programmed via the I registers can be accessed via the 2-wire I 2 actions. The I C-bus address of the TZA3015HW can be found in Table 2. 2 Table 21 I C-bus registers ADDRESS NAME (HEX) General part 00 ...

Page 33

... C junction temperature <130 C loss of lock synthesizer out of lock synthesizer out of lock FIFO overflow or underflow FIFO overflow or underflow occurred FIFO normal operating 33 Preliminary specification TZA3015HW DEFAULT RANGE 0010 0000 n.a. 0000 0000 n.a. 0000 0001 128 to 255 0000 0000 ...

Page 34

... LOL signal not masked masked; note 1 mask FIFO overflow or underflow not masked masked; note Preliminary specification TZA3015HW PARAMETER NAME LOS INWINDOW TALARM LOL reserved OVERFLOW PARAMETER NAME MLOS MINWINDOW ...

Page 35

... Preliminary specification TZA3015HW PARAMETER NAME FREFI2C[2:0] 2 C-bus I2CFREF reserved CLUPPLLHG CLUPPLLINV CLUPPLLEN default value PARAMETER NAME LM[2:0] ...

Page 36

... DESCRIPTION interrupt output polarity 1 inverted 0 normal operating interrupt output configuration 1 push-pull output 0 open drain output Preliminary specification TZA3015HW PARAMETER NAME 2 C-bus I2CLM reserved ENRX ENTX 2 C-bus I2CENTRX default value PARAMETER NAME reserved LOWSWING 2 C-bus I2CLOWSWING default value ...

Page 37

... DESCRIPTION x x don’t care; HX31 = MSB DESCRIPTION x x don’t care Preliminary specification TZA3015HW PARAMETER NAME H[31:24] default value PARAMETER NAME H[23:16] default value PARAMETER NAME H[15:08] default value PARAMETER NAME H[07:00] default value PARAMETER NAME HX[31:24] default value ...

Page 38

... ENBA programming enable I C-bus programming enable programming by pins Preliminary specification TZA3015HW PARAMETER HX[15:08] default value PARAMETER HX[07:00] default value PARAMETER reserved RXBUSSWAP DMXMUTE ENBA 2 C-bus ...

Page 39

... N; RXN0 = LSB DESCRIPTION x x fractional divider; RXK21 = MSB RXNILFRAC control bit (NF) no fractional N functionality fractional N functionality Preliminary specification TZA3015HW PARAMETER NAME RXDIV_M[2:0] reserved default value PARAMETER NAME RXN8 reserved default value PARAMETER NAME RXN[7:0] default value PARAMETER ...

Page 40

... DESCRIPTION enable loss of signal detection 1 LOS detection enabled 0 LOS detection disabled 40 Preliminary specification TZA3015HW PARAMETER NAME RXK[15:8] default value PARAMETER NAME RXK[7:0] default value PARAMETER NAME WINSIZE[2:0] WINSIZE I2CWINSIZE AUTOWIN reserved ...

Page 41

... Mbit octave number 2; 450 to 900 Mbit octave number 3; 225 to 450 Mbit octave number 225 Mbit Preliminary specification TZA3015HW PARAMETER NAME 2 C-bus I2CLOSTH HTLCB[2:0] SLEN SLSGN LOSPOL default value PARAMETER NAME AMP[2:0] ...

Page 42

... DESCRIPTION x x invert RX prescaler output inverted normal enable RX prescaler output enabled disabled 42 Preliminary specification TZA3015HW PARAMETER NAME RXPDINV RXPDEN RXPCINV RXPCEN RXPARINV RXPAREN RXFPINV RXFPEN default value PARAMETER NAME reserved RXPRSCLINV RXPRSCLEN ...

Page 43

... DESCRIPTION x division ratio divider N; TXN8 = MSB DESCRIPTION x x division ratio divider N; TXN0 = LSB Preliminary specification TZA3015HW PARAMETER NAME RXPCDDREN I2CDDR default value PARAMETER NAME TXDIV_M[2:0] reserved default value PARAMETER NAME TXN8 reserved default value PARAMETER NAME ...

Page 44

... C-bus interface by external pin PAREVEN parallel clock input polarity inverted normal 44 Preliminary specification TZA3015HW PARAMETER TXK[21:16] reserved TXNILFRAC default value PARAMETER TXK[15:8] default value PARAMETER TXK[7:0] default value PARAMETER TXBUSSWAP TXPAREVEN ...

Page 45

... FIFO reset programming C-bus interface by external pin FIFORESET DDR clock frequency mode for TXPC DDR mode enabled normal mode Preliminary specification TZA3015HW PARAMETER NAME TXPDINV reserved default value PARAMETER NAME TXPCOPHASE CLKDIR 2 C-bus I2CLKDIR FIFORESET ...

Page 46

... Preliminary specification TZA3015HW PARAMETER NAME reserved TXPCODDREN TXPCOINV TXPCOEN TXPRSCLINV TXPRSCLEN TXPARERRINV TXPARERREN ...

Page 47

... DESCRIPTION serial output signal amplitude 0 0 minimum (p- default; 300 mV (p- maximum; 1100 mV (p-p) serial output termination AC-coupled DC-coupled Preliminary specification TZA3015HW PARAMETER NAME TXSCINV TXSCEN 2 C-bus I2CTXSCEN default value PARAMETER NAME RFS[3:0] reserved RFOUTTERMAC reserved default value ...

Page 48

... In compliance with JEDEC standards JESD51-5 and JESD51-7. 2. Four-layer Printed-Circuit Board (PCB) in still air with 36 plated vias connected with the heatsink and the second and fourth layer in the PCB. 2003 Dec 16 PARAMETER CONDITIONS notes 1 and 2 48 Preliminary specification TZA3015HW MIN. MAX. UNIT 0.5 +3.6 V 0.5 +3 ...

Page 49

... single-ended with 50 220 external load; DC swing; note 20% to 80% 49 Preliminary specification TZA3015HW < 16 K/W; all characteristics are specified for the ; positive currents flow into the device; unless TYP. MAX 395 456 0 471 550 1.6 1 ...

Page 50

... DDR mode; see Fig. clk normal mode 45 DDR mode 47 normal mode 45 DDR mode 47 RXPD0 to RXPD3, RXPAR and RXFP; note 100 50 Preliminary specification TZA3015HW TYP. MAX + 3200 500 5 12 +50 100 120 3200 300 360 500 600 1.22 1.33 200 ...

Page 51

... Fig. 124 Mbit/s; bit see Fig.29; note 6 see Fig.29 see Fig.29 note 6 40 single-ended 50 note single-ended Preliminary specification TZA3015HW TYP. MAX. 1000 100 120 150 300 20 300 1100 850 1300 1450 0. 0.3T + 240 clk clk ...

Page 52

... mV PRBS(2 1) input 30 to 3200 Mbit/ PRBS(2 1 3. 120 C note i(p- i(p-p) CLUPPLLHG = 0 CLUPPLLHG = 1 CLUPPLLHG = 0 CLUPPLLHG = 1 52 Preliminary specification TZA3015HW TYP. MAX. +20 R 19. 1.21 1.26 500 17 20 680 780 + 0 0.1 1 0.1 1 UNIT ppm ...

Page 53

... MHz kHz to 5 MHz f = 250 kHz to 5 MHz STM16/OC48 mode; note kHz to 20 MHz kHz to 20 MHz MHz to 20 MHz 30 Mbit/s; note 6 30 Mbit/s; note 6 30 Mbit/s; note 6 0. Preliminary specification TZA3015HW TYP. MAX. >10 >1 >0.5 >10 >1 >0 0 ...

Page 54

... LOWSWING = LOW (high swing for LVDS outputs); bits RFS[3:0] = 1111 (maximum output swing for TXSD(Q) and 2003 Dec 16 CONDITIONS MIN. note 6 0.05V 1.3 0.6 0.6 0.6 0 100 0 1.3 0 0. Preliminary specification TZA3015HW TYP. MAX. CC 0.4 +10 10 100 0.9 300 300 400 50 UNIT kHz ...

Page 55

... LOSTH serial output clock enabled 1000 ppm automatic byte alignment even parity AC-coupled 19.44 MHz input STM16; PRBS (2 1) 100 differential outputs open circuit normal mode co-directional clocking external load not loaded 55 Preliminary specification TZA3015HW = 680 mA, CCD = 0.2 V (p-p) single-ended i ...

Page 56

... The timing is measured from the crossover point of the reference signal to the crossover point of the input. Fig.29 Parallel bus co-directional (TXPC) and contra-directional (TXPCO) timing. 2003 Dec 16 t D-C Fig.27 Serial bus output timing. RXPC t D-C Fig.28 Parallel bus output timing. T clk t su valid data 56 Preliminary specification TZA3015HW MGX390 MGX478 t h MCE422 ...

Page 57

... 116.7nF ------------------------------------------------- - 2500 = 1 mA yields R = 7854 CP and , if R and C1 are known, use the -3dB VCXO CP = ------------------------------------------ - 2 RDIV VCXO CP ---------------------------------------------- - --- - RDIV 2 TZA3015HW = 2000 Hz/V. VCXO = 10 kHz. 3dB(VCXO) should be 3dB < 5 kHz. To cope with = 2.5 kHz is chosen. and ...

Page 58

... SWING CONTROL I swing in 2003 Dec dB/decade Fig.30 Clean-up PLL jitter transfer OUT OUTQ on-chip off-chip Fig.31 Serial RF output (AC-coupled). 58 Preliminary specification TZA3015HW MCE423 (VCXO) log(f) [Hz] 40 dB/decade V bias 50 50 transmission lines to high- 50 impedance 50 input MDB068 ...

Page 59

... SWING CONTROL I swing in handbook, halfpage 2003 Dec transmission OUT OUTQ on-chip off-chip Fig.32 Serial RF output (DC-coupled). V CCD D 50 300 50 1 MGX391 Fig.33 LVDS input. 59 Preliminary specification TZA3015HW 50 50 lines to high- 50 impedance 50 input MDB069 ...

Page 60

... COMMON MODE CONTROL V ref in swing-setting 2003 Dec 16 in swing-setting on-chip Fig.34 LVDS output (DC-coupled OUT OUTQ on-chip Fig.35 LVDS output (AC-coupled). 60 Preliminary specification TZA3015HW V CC transmission lines OUT 50 100 impedance OUTQ 50 off-chip AC transmission coupling 50 lines 50 50 ...

Page 61

... Philips Semiconductors 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver 2003 Dec CREF 50 CREFQ V EE Fig.36 Reference clock input. 61 Preliminary specification TZA3015HW 001aaa056 ...

Page 62

... scale (1) ( 0.20 14.1 7.1 14.1 7.1 0.5 0.09 13.9 6.1 13.9 6.1 REFERENCES JEDEC JEITA 62 Preliminary specification detail 16.15 16.15 0.75 1 0.2 0.08 15.85 15.85 0.45 EUROPEAN PROJECTION TZA3015HW SOT638 (1) ( 1.15 1.15 7 0.08 0.85 0.85 0 ISSUE DATE 01-03-30 03-04-07 ...

Page 63

... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 63 Preliminary specification TZA3015HW ...

Page 64

... Hot bar or manual soldering is suitable for PMFP packages. ADDITIONAL SOLDERING INFORMATION The die pad has to be soldered to the PCB for thermal and grounding reasons. 2003 Dec 16 (1) (3) , TFBGA, (8) 64 Preliminary specification TZA3015HW SOLDERING METHOD WAVE REFLOW not suitable suitable (4) not suitable suitable suitable ...

Page 65

... Preliminary specification TZA3015HW DEFINITION These products are not Philips Semiconductors ...

Page 66

... I Philips. This specification can be ordered using the code 9398 393 40011. 2003 Dec components conveys a license under the Philips’ system provided the system conforms to the I 66 Preliminary specification TZA3015HW 2 C patent to use the 2 C specification defined by ...

Page 67

Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2003 All rights are reserved. Reproduction in whole or in part is prohibited ...

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