sc4525c Semtech Corporation, sc4525c Datasheet - Page 13

• Manufacturer Part Number: sc4525c
• Description: 28v 3a Step-down Switching Regulator
• Manufacturer: Semtech Corporation

D
D
C
C
O
O
20
20






+
+
D ⋅
D ⋅
O
O
=
=
I
I
1
1
V
V
O
O
L
L
+
+
V
V
O
O
V
V
0 .
0 .
+
+
I
I
%
%


 
 


⋅
⋅
V
V
D
D
O
O
F
F
V
V
O
O
I
I
+
+


 
 


Applications Information (Cont.)
Figure 6(b) and (c). Methods of Bootstrapping the
SC4525C
Loop Compensation
The goal of compensation is to shape the frequency
response of the converter so as to achieve high DC
accuracy and fast transient response while maintaining
loop stability.
IN
IN
D
D
O
O
V
V
SW
SW
V
V
⋅
⋅
−
−
⋅
⋅
ESR
ESR
I
I
D
D
V
V
)
)
O
O
⋅
⋅
−
−
V
V
⋅
⋅
D
D
)
)
F
F
⋅
⋅
D
D
1 (
1 (
⋅
⋅
CESAT
CESAT
⋅
⋅
FB
FB
1
1
L
L
F
F
SW
SW
1 (
1 (
⋅
⋅
1
1
SW
SW
+
+






−
−
1 (
1 (
VIN
VIN
REF
REF
−
−
) D
) D
8
8
Figure 7. Block diagram of control loops
−
−
) D
) D
⋅
⋅
F
F
+
+
) D
) D
-
-
CONTROLLER AND SCHOTTKY DIODE
CONTROLLER AND SCHOTTKY DIODE
SW
SW
1
1
EA
EA
R
R
R
R
D3
D3
D4 is either a pn juntion diode or a Schottky diode
D
D
D
D
L
L
L
L
I
I
I
I
C
C
D
D
D
D
D
D
D
D
C
C
C5
C5
R7
R7
RMS
RMS
RMS
RMS
⋅
⋅
4
4
4
4
1
1
1
1
I
I
V
V
I
I
V
V
IN
IN
IN
IN
IN
C
C
=
=
=
=
IN
L
L
L
L
depending on the operating temperature.
=
=
=
=
O
O
O
O
=
=
=
=
SC4525C
O
O
COMP
COMP
=
=
=
=
_
_
_
_
>
>
>
>
V
V
V
V
R
R
R
R
SC4525C
=
=
=
=
CIN
CIN
CIN
CIN
D1
D1
V (
V (
V (
V (


 
 


Vramp
Vramp
IN
IN
IN
IN
Vc
Vc
6
6
6
6
V (
V (
V (
V (
GND
4
4
4
4
BST
BST
D
D
D
D
GND
O
O
20
20
20
20












O
O
+
+
+
+
D ⋅
D ⋅
D ⋅
D ⋅
O
O
O
O
=
=
=
=
I
I
I
I
1
1
1
1
V
V
V
V
L
L
L
L
+
+
+
+
V
V
R
R
C
C
C
C
G
G
R
R
C8
C8
A
A
V
V
A
A
C
C
C
C
O
O
CA
CA
O
O
V
V
V
V
V
V
V
V
0 .
0 .
+
+
I
I
MODULATOR
MODULATOR
0 .
0 .
+
+
%
%
%
%
I
I
⋅
⋅
⋅
⋅
V
V
D
D
D
D
O
O
O
O
V
V
F
F
F
F
SW
V
V
V
V
7
7
7
7
O
O
5
5
o
o
c
c
PWM
PWM
5
5
O
O
C
C
C
C
8
8
8
8
SW
I
I
I
I
+
+
+
+




 
 
 
 




IN
IN
IN
IN
O
O
PWM
PWM
V
V
V
V
SW
SW
SW
SW
D
D
D
D
O
O
V
V
V
V
⋅
⋅
⋅
⋅
−
−
−
−
⋅
⋅
⋅
⋅
(C)
ESR
ESR
ESR
ESR
=
=
(b)
(b)
=
=
=
=
=
=
=
=
I
I
I
I
=
=
=
=
=
=
=
=
D
D
V
V
D
D
)
)
)
)
V
V
O
O
O
O
⋅
⋅
⋅
⋅
−
−
−
−
V
V
V
V
⋅
⋅
⋅
⋅
D
D
D
D
)
)
)
)
10
10
. 0
. 0
1 (
1 (
F
F
F
F
⋅
⋅
2
2
D
D
2
2
−
−
−
−
⋅
⋅
1 (
1 (
⋅
⋅
D
D
2
2
2
2
1 (
1 (
⋅
⋅
≈
≈
Rs
Rs
CESAT
CESAT
CESAT
CESAT
⋅
⋅
1
1
⋅
⋅
1
1
L
L
L
L
F
F
F
F
g
g
SW
SW
SW
SW
⋅ π
⋅ π
1 (
1 (
1 (
1 (
π
π
20
20
20
20
28
28
⋅ π
⋅ π
π
π
D4
⋅
⋅
⋅
⋅
1
1
SW
SW
SW
SW
+
+
1
1
+
+
+
+
G
G
m
m












10
10
−
−
−
−
1 (
1 (
1 (
1 (
A
A
20
20
F
F
F
F
C
C
CA
CA
1
1
1
1
Io
Io
16
16
600
600
−
−
) D
) D
/ s
/ s
1 Z
1 Z
P
P
−
−
) D
) D
D2
8
8
8
8
D 2
D 2
1
1
⋅
⋅
⋅
⋅
⋅
⋅
R
R
−
−
−
−
15
15
) D
) D
) D
) D
log
log
log
log
10
10
⋅
⋅
20
20
⋅
⋅
⋅
⋅
R
R
R
R
C1
G
G
9 .
9 .
F
F
F
F
R
R
) D
) D
) D
) D
ω
ω
⋅
⋅
C1
SW
SW
10
10
7
7
7
7
SW
SW
SW
SW
PWM
PWM
S
S
p
p
⋅
⋅
D1
1
1
1
1


 
 








−
−
10
10
1 ( )
1 ( )
3
3
,
,
G
G
28
28
3
3
⋅
⋅
⋅
⋅
1
1
1 (
1 (
CA
CA
=
=
1
1
C
C
C
C
3
3
1
1
⋅
⋅
+
+
⋅
⋅
22
22
22
22
O
O
O
O
L1
L1
R
R
⋅
⋅
+
+
R
R
R
R
C
C
C
C
G
G
C
C
C
C
6
6
A
A
A
A
/ s
/ s
V
V
V
V
22
22
VOUT>8V




 
 
 
 




Co
Co
Resr
Resr
S
S
1 .
1 .
7
7
o
o
c
c
PWM
PWM
7
7
C
C
C
C
5
5
R s
R s
8
8
5
5
8
8
VOUT
.
.
1 .
1 .
1
1
k 3
k 3
⋅
⋅
ω
ω
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
1 .
1 .
2
2
⋅
⋅
ESR
ESR
⋅
⋅
n
n
10
10
ω
ω
10
10
. 0
. 0
1 (
1 (
10
10
π
π
−
−
−
−
2
2
2
2
2
2
2
2
≈
≈
Q
Q
⋅
⋅
g
g
F
F
p
p
10
10
⋅ π
⋅ π
C
C
π
π
1
1
20
20
20
20
28
28
⋅ π
⋅ π
π
π
G
G
+
+
+
+
m
m
C
C
−
−
10
10
≈
≈
A
A
3
3
20
20
F
F
F
F
O
O
3
3
C
C
C
C
Vo
Vo
CA
CA
1
1
1
1
16
16
600
600
s
s
/ s
/ s
1 Z
1 Z
P
P
3
3
)
)
R4
R4
R6
R6
R
R
=
=
⋅
⋅
⋅
⋅
1
1
O
O
⋅
⋅
R
R
⋅
⋅
2
2
15
15
log
log
log
log
10
10
20
20
1
1
⋅
⋅
C
C
2
2
=
=
R
R
R
R
. 0
. 0
G
G
9 .
9 .
/
/
R
R
⋅
⋅
ω
ω
⋅
⋅
O
O
⋅ π
⋅ π
10
10
7
7
7
7
12
12
ω
ω
PWM
PWM
V
V
S
S
p
p
V
V
⋅
⋅
45
45


 
 








−
−
,
,
FB
FB
10
10
1 ( )
1 ( )
O
O
3
3
2
2
n
n
,
,
G
G
28
28
80
80
pF
pF
)
)
3
3
1
1
nF
nF
1 (
1 (
=
=


 
 


CA
CA
1
1
3
3
1
1
⋅
⋅
+
+
The block diagram in Figure 7 shows the control loops of a
buck converter with the SC4525C. The inner loop (current
loop) consists of a current sensing resistor (R
and a current amplifier (CA) with gain (G
outer loop (voltage loop) consists of an error amplifier
(EA), a PWM modulator, and a LC filter.
Since the current loop is internally closed, the remaining
task for the loop compensation is to design the voltage
compensator (C
For a converter with switching frequency F
inductance L
control (V
given by:
This transfer function has a finite DC gain
an ESR zero F
a dominant low-frequency pole F
and double poles at half the switching frequency.
Including the voltage divider (R
feedback transfer function is found and plotted in Figure
8 as the converter gain.
Since the converter gain has only one dominant pole at
low frequency, a simple Type-2 compensation network
is sufficient for voltage loop compensation. As shown in
Figure 8, the voltage compensator has a low frequency
integrator pole, a zero at F
at F
frequency. The zero is introduced to compensate the
excessive phase lag at the loop gain crossover due to the
integrator pole (-90deg) and the dominant pole (-90deg).
⋅
⋅
22
22
22
22
⋅
⋅
R
R
⋅
⋅
+
+
10
10
6
6
/ s
/ s
22
22
S
S
1 .
1 .
R s
R s
.
.
1 .
1 .
1
1
1
1
k 3
k 3
P1
⋅
⋅
ω
ω
3
3
1 .
1 .
2
2
⋅
⋅
ESR
ESR
. The integrator is used to boost the gain at low
⋅
⋅
R
R
R
R
n
n
R
R
⋅
⋅
C
C
C
C
C
C
C
C
10
10
G
G
G
G
R
R
ω
ω
C
C
C
C
C
C
C
C
A
A
A
A
A
A
A
A
ω
ω
V
V
V
V
V
V
V
V
10
10
π
π
22
22
Q
Q
⋅
⋅
7
7
7
7
o
o
o
o
c
c
PWM
PWM
PWM
PWM
7
7
7
7
C
C
C
C
C
C
C
C
5
5
5
5
8
8
8
8
c
c
Z
Z
5
5
5
5
8
8
8
8
p
p
F
F
10
10
C
C
1
1
+
+
C
C
−
−
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
≈
≈
=
=
3
3
=
=
C
O
O
3
3
C
C
⋅
⋅
) to output (V
s
s
)
)
10
10
3
3
. 0
. 0
1 (
1 (
10
10
10
10
R
R
. 0
. 0
1 (
1 (
R
R
−
−
−
−
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
−
−
−
−
=
=
≈
≈
O
O
≈
≈
⋅
⋅
2
2
g
g
g
g
1
1
⋅ π
⋅ π
ESR
ESR
C
C
⋅ π
⋅ π
1
=
=
Z
2
2
π
π
20
20
20
20
28
28
⋅ π
⋅ π
⋅ π
⋅ π
π
π
π
π
π
π
20
20
20
20
28
28
. 0
. 0
/
/
⋅
⋅
, output capacitance C
G
G
G
G
+
+
+
+
m
m
m
m
10
10
10
10
−
−
1
1
A
A
at
O
O
⋅ π
⋅ π
A
A
20
20
20
20
F
F
F
F
F
F
F
F
12
12
ω
ω
V
V
6
6
C
C
C
C
V
V
CA
CA
CA
CA
1
1
1
1
16
16
600
600
45
45
1
1
1
1
16
16
600
600
/ s
/ s
/ s
/ s
C
C
1 Z
1 Z
P
P
5
1 Z
1 Z
P
P
,
,
FB
FB
, R
⋅
⋅
⋅
⋅
2
2
n
n
1
1
1
1
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
O
O
R
R
R
R
⋅
⋅
15
15
O
O
15
15
80
80
log
log
log
log
log
log
log
log
10
10
10
10
pF
pF
20
20
20
20
⋅
⋅
⋅
⋅
)
)
1
1
R
R
R
R
R
R
R
R
3
3
nF
nF
G
G
G
G
9 .
9 .
9 .
9 .
R
R
R
R
12
12
12
12
ω
ω
ω
ω


 
 
7


⋅
⋅
,
,
⋅
⋅
0 .
0 .
3 .
3 .
, and C
10
10
7
7
7
7
7
7
10
10
7
7
PWM
PWM
PWM
PWM
S
S
p
p
S
S
⋅
⋅
⋅
⋅
p
p
⋅
⋅




 
 
 
 
















−
−
−
−
10
10
10
10
10
10
1 ( )
1 ( )
1 ( )
1 ( )
3
3
,
,
3
3
,
,
G
G
28
28
G
G
28
28






3
3
3
3
1
1
1
1
1 (
1 (
=
=
=
=
=
=
1 (
1 (
CA
CA
CA
CA
1
1
1
1
1
1
3
3
3
3
1
1
⋅
⋅
⋅
⋅
1
1
3
3
O
+
+
+
+
15
15
⋅
⋅
⋅
⋅
22
22
22
22
22
22
22
22
R
R
) transfer function in Figure 7 is
R
R
⋅
⋅
⋅
⋅
+
+
+
+
⋅
⋅
ω
ω
6
6
6
6
/ s
/ s
8
/ s
/ s
22
22
22
22
S
S
).
22
22
S
S
Z1
1 .
1 .
1 .
1 .
R s
R s
R s
R s
Z
Z
9 .
9 .
.
.
1 .
1 .
1
1
.
.
1 .
1 .
1
1
, and a high frequency pole
k 3
k 3
k 3
k 3
⋅
⋅
⋅
⋅
ω
ω
ω
ω
=
=
1 .
1 .
1 .
1 .
dB
dB
2
2
2
2
⋅
⋅
⋅
⋅
⋅
⋅
ESR
ESR
ESR
ESR
⋅
⋅
⋅
⋅
n
n
n
n
10
10
10
10
10
10
ω
ω
ω
ω
R
R
π
π
π
π
10
10
10
10
Q
Q
Q
Q
⋅
⋅
⋅
⋅
4
p
p
F
F
F
F
10
10
p
p
10
10
ESR
ESR
C
C
C
C
P
1
1
1
1
+
+
+
+
C
C
−
−
C
C
−
−
1
1
and R
−
−
≈
≈
3
3
3
3
≈
≈
at
O
O
O
O
3
3
3
3
C
C
C
C
6
6
s
s
C
C
s
s
)
)
3
3
3
3
)
)
R
R
R
R
=
=
=
=
O
O
O
O
O
⋅
⋅
⋅
⋅
2
2
⋅
⋅
2
2
O
O
1
1
1
1
C
C
C
C
=
=
2
2
2
2
1
1
=
=
3
3
. 0
. 0
. 0
. 0
and loading R, the
/
/
/
/
⋅
⋅
⋅
⋅
,
,
O
O
⋅ π
⋅ π
O
O
⋅ π
⋅ π
0 .
0 .
12
12
12
12
3 .
3 .
ω
ω
V
V
V
V
ω
ω
6
V
V
V
V
45
45
45
45
,
,
,
,
), the control to
FB
FB
FB
FB
2
2
n
n
n
n
SC4525C
O
O
O
O
2
2






80
80
80
80
pF
pF
pF
pF
)
)
)
)
nF
nF
nF
nF
=
=




 
 
 
 




CA
15
15
⋅
⋅
⋅
⋅
=18.5). The
10
10
10
10
s
SW
=3.53mW)
(8)
9 .
9 .
, output
1
1
1
1
3
3
3
3
dB
dB
⋅
⋅
⋅
⋅
ω
ω
ω
ω
22
22
22
22
Z
Z
Z
Z
=
=
=
=
13
⋅
⋅
⋅
⋅
10
10
10
10
R
R
R
R
ESR
ESR
ESR
ESR
1
1
1
1
−
−
−
−
6
6
6
6
C
C
C
C
⋅
⋅
⋅
⋅
O
O
O
O
1
1
1
1
. 3
. 3
3
3
,
,
,
,
0 .
0 .
0 .
0 .
3 .
3 .