l6390 STMicroelectronics, l6390 Datasheet
l6390
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l6390 Summary of contents
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... This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. High-voltage high and low side driver SO-16 Description The L6390 is a high-voltage device manufactured with the BCD "OFF-LINE" technology monolithic half-bridge gate driver for N-channel Power MOSFET or IGBT. The high side (floating) section is designed to stand a voltage rail up to 600 V ...
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... Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 Smart shut down function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.1 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10 Package mecanichal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2/22 L6390 ...
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... L6390 1 Block diagram Figure 1. Block diagram 4 VCC 3 HIN 5V 1 LIN 2 SD/OD 8 GND OPOUT BOOTSTRAP DRIVER from LVG UV DETECTION LOGIC SHOOT THROUGH PREVENTION SD LATCH SMART SD DEAD TIME Block diagram FLOATING STRUCTURE 16 UV DETECTION HVG DRIVER S 15 LEVEL SHIFTER LVG ...
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... Opamp non inverting input CP+ I Comparator input (1) O Low side driver output NC Not connected OUT P High side (Floating) common voltage (1) O High side driver output P Bootstrap supply voltage BOOT 16 15 HVG 14 OUT LVG 10 CP+ OP+ 9 Function > This CC L6390 ...
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... L6390 3 Truth table Table 3. Truth table Input LIN HIN Truth table Output LVG HVG 5/22 ...
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... Storage temperature stg Note: ESD immunity for pins 14, 15 and 16 is guaranteed up to TBD (Human Body Model) 4.2 Thermal data Table 5. Thermal data Symbol R Thermal resistance junction to ambient th(JA) 6/22 Parameter = 85 °C) A Parameter L6390 Value 0.3 boot boot - 0 -0 +0 +0 ...
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... L6390 4.3 Recommended operating conditions Table 6. Recommended operating conditions Symbol Pin V 14 Output voltage out ( Floating supply voltage BS f Switching frequency Supply voltage cc Junction temperature the condition TBD V < 580V boot out Parameter Test condition ...
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... Fall time +25 ° Min Typ Max 125 cc 125 125 180 = 1 nF nF nF nF nF, L TBD = 1 nF, L TBD = 1 nF, L TBD 75 35 L6390 Unit µs µs µs µ ...
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... L6390 Figure 3. Timing LIN LVG HIN HVG SD LVG/HVG 50 90 90 90% 10 Electrical characteristics 50 90% 10% t off 50 90% 10% t off 50 90% 10% t off 9/22 ...
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... LVG ON <10 µ (tp<10 µ °C) J Min Typ Max 700 1400 11.8 10.4 120 150 720 1100 0.53 700 1400 11.6 10.2 70 110 152 = 600 V 10 120 270 430 L6390 Unit µA µ µA µA µA Ω ...
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... L6390 Table 8. DC operation electrical characteristics (V Symbol Pin Parameter Logic inputs Low level logic threshold V il voltage High level logic threshold V ih voltage HIN logic “1” input bias I HINh current 3 HIN logic “0” input bias I HINl current LIN logic “1” input bias ...
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... C = 180 nF kΩ Min Typ Max 3 15 200 TBD 180 360 13.5 14 2.5 3.8 TBD 100 = +25 °C) Min Typ Max 1 0.5 115 210 60 L6390 Unit V/µs MHz Unit µ V/µsec ...
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... L6390 6 Waveforms definitions Figure 4. Dead time and interlocking waveforms definitions CONTROL SIGNAL EDGES OVERLAPPED: INTERLOCKING + DEAD TIME CONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIME CONTROL SIGNALS EDGES NOT OVERLAPPED, BUT INSIDE THE DEAD TIME: DEAD TIME CONTROL SIGNALS EDGES NOT OVERLAPPED, OUTSIDE THE DEAD TIME: ...
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... Smart shut down function 7 Smart shut down function L6390 integrates a comparator committed to the fault sensing function. The comparator has an internal voltage reference Vref connected to its inverting input, while the non-inverting input is available on pin 10. The comparator input can be connected to an external shunt resistor in order to implement a simple over-current detection function ...
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... SD input and an RC network is connected to this SD/OD line in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition. Differently from the common fault detection systems, L6390 Smart Shut Down architecture allows to immediately turn-off the output gate driver in case of fault, by minimizing the propagation delay between the fault detection event and the actual outputs switch-off ...
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... FLOATING STRUCTURE 4 from LVG UV DETECTION 3 LEVEL SHIFTER LOGIC 5V SHOOT THROUGH PREVENTION LATCH SMART SD COMPARATOR 8 DEAD 5 TIME 7 16 BOOT UV DETECTION HVG DRIVER S HVG OUT V CC LVG DRIVER LVG CP BIAS REF VCC 9 OP+ OPAMP + OP L6390 H.V. Cboot TO LOAD ...
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... This charge µF capacitor means a voltage drop of 1V. EXT is close to GND (or lower) and in the meanwhile the OUT ) of the C charge BOOT Bootstrap driver (Figure 7.a). In the L6390 a patented gate gate is proportional to the cyclical voltage loss. EXT = 100 nF the drop would be BOOT selection has to take into account also is 5 ms, C ...
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... In fact: charge 30nC -------------- - 125Ω 0. drop 5µs BOOT H.V. HVG C BOOT V OUT TO LOAD LVG a Q gate ------------------ drop dson T ch arg e is the on resistance of the dson ⋅ ∼ is calculated: if this drop BOOT BOOT V S HVG V OUT LVG b L6390 H.V. C BOOT TO LOAD D99IN1067 ...
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... L6390 10 Package mecanichal data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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... OUTLINE AND MECHANICAL DATA PACKAGE AND PACKING INFORMATION 16-LEAD SMALL OUTLINE PACKAGE Weight: not available SO-16 SO16 (Narrow) 0016020 D L6390 ...
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... L6390 11 Revision history Table 11. Document revision history Date 29-Feb-2008 Revision 1 First release Revision history Changes 21/22 ...
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