hip4020 Intersil Corporation, hip4020 Datasheet

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hip4020

Manufacturer Part Number
hip4020
Description
Full Bridge Driver With Integrated 0.5a Power Fets For Small 3v, 5v And 12v Dc Motors
Manufacturer
Intersil Corporation
Datasheet

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Half Amp Full Bridge Power Driver for
Small 3V, 5V and 12V DC Motors
In the Functional Block Diagram of the HIP4020, the four
switches and a load are arranged in an H-Configuration so
that the drive voltage from terminals OUTA and OUTB can
be cross-switched to change the direction of current flow in
the load. This is commonly known as 4-quadrant load
control. As shown in the Block Diagram, switches Q1 and Q4
are conducting or in an ON state when current flows from
V
V
with respect to OUTB. Switches Q1 and Q4 are operated
synchronously by the control logic. The control logic
switches Q3 and Q2 to an open or OFF state when Q1 and
Q4 are switched ON. To reverse the current flow in the load,
the switch states are reversed where Q1 and Q4 are OFF
while Q2 and Q3 are ON. Consequently, current then flows
from V
terminal V
potential with respect to OUTA.
Terminals ENA and ENB are ENABLE Inputs for the Logic A
and B Input Controls. The ILF output is an Overcurrent Limit
Fault Flag Output and indicates a fault condition for either
Output A or B or both. The V
Supply reference terminals for the A and B Control Logic
Inputs and ILF Output. While the V
terminal is internally connected to each bridge driver, the
V
independent from V
V
the gate drive circuitry to the NMOS (low-side) output stages
allows controlled level shifting of the output drive relative to
ground.
DD
SSB
SSA
SS
ground reference terminal. The use of level shifters in
through Q1 to the load, and then through Q4 to terminal
; where load terminal OUTA is at a positive potential
and V
DD
through Q3, through the load, and through Q2 to
SSA
SSB
, and load terminal OUTB is then at a positive
Power Supply terminals are separate and
SS
and may be more negative than the
®
DD
1
and V
DD
Data Sheet
SS
positive power supply
are the Power
1-888-INTERSIL or 1-888-468-3774
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• Two Independent Controlled Complementary MOS Power
• Split ±Voltage Power Supply Option for Output Drivers
• Load Switching Capabilities to 0.5A
• Single Supply Range +2.5V to +15V
• Low Standby Current
• CMOS/TTL Compatible Input Logic
• Over-Temperature Shutdown Protection
• Overcurrent Limit Protection
• Overcurrent Fault Flag Output
• Direction, Braking and PWM Control
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• DC Motor Driver
• Relay and Solenoid Drivers
• Stepper Motor Controller
• Air Core Gauge Instrument Driver
• Speedometer Displays
• Tachometer Displays
• Remote Power Switch
• Battery Operated Switch Circuits
• Logic and Microcontroller Operated Switch
Ordering Information
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
HIP4020IB
HIP4020IBZ
(Note)
HIP4020IBZT
(Note)
December 20, 2005
Output Half H-Drivers (Full-Bridge) for Nominal 3V to 12V
Power Supply Operation
NUMBER
PART
All other trademarks mentioned are the property of their respective owners.
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
HIP4020IB
HIP4020IBZ
HIP4020IBZ
MARKING
Copyright Intersil Americas Inc. 1997, 2005. All Rights Reserved
PART
RANGE (°C)
-40 to 85
-40 to 85
-40 to 85
TEMP.
20 Ld SOIC
20 Ld SOIC
(Pb-free)
20 Ld SOIC
Tape and Reel
(Pb-free)
PACKAGE
HIP4020
FN3976.3
DWG. #
M20.3
M20.3
M20.3
PKG.

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hip4020 Summary of contents

Page 1

... Data Sheet Half Amp Full Bridge Power Driver for Small 3V, 5V and 12V DC Motors In the Functional Block Diagram of the HIP4020, the four switches and a load are arranged in an H-Configuration so that the drive voltage from terminals OUTA and OUTB can be cross-switched to change the direction of current flow in the load ...

Page 2

... Pinout HIP4020 (SOIC) TOP VIEW ILF ENB 4 17 OUTB SSB SSA ENA OUTA HIP4020 Block Diagram I SENSE ENB ENA I SENSE ILF ...

Page 3

... OUTA, OUTB Source Current Limiting OUTA, OUTB Sink Current Limiting OUTA, OUTB Source Current Limiting OUTA, OUTB Sink Current Limiting 3 HIP4020 Thermal Information . . . . . . . . . . . . .+15V Thermal Resistance (Typical, Note (Note 1) Plastic SOIC Package . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

... Respectively, Switch Driver A and Switch Driver B Output pins. 2 ILF Current Limiting Fault Output Flag pin; when in a high logic state, signifies that Switch Driver both are in a Current Limiting Fault Mode. 4 HIP4020 = +5V 0V, Unless Otherwise Specified (Continued) DD SSA ...

Page 5

... OH = Output High (sourcing current to the output terminal Output Low (sinking current from the output terminal Don’t Care Application The HIP4020 is designed to detect load current feedback from sampling resistors of low value in the source connections of the output drivers to V (See Figure 1). When the sink or source current at OUTA or OUTB exceeds the preset OC (Overcurrent) limiting value of 550mA typical, the current is held at the limiting value ...

Page 6

... B2 (BRAKE) ENB (ENABLE) FIGURE 4. EQUIVALENT CONTROL LOGIC A AND B SHOWN DRIVING THE OUTA AND OUTB OUTPUT DRIVERS 6 HIP4020 V ground reference terminal. However, the maximum SS supply level from V than the Absolute Maximum Supply Voltage rating. Terminals A1, B1, A2, B2, ENA and ENB are internally connected to protection circuits intended to guard the CMOS gate-oxides against damage due to electrostatic discharge ...

Page 7

... FIGURE 7. TYPICAL CHARACTERISTIC OF THE P AND N OUTPUT DRIVER SHORT CIRCUIT CURRENT vs SUPPLY VOLTAGE 25°C AMBIENT 7 HIP4020 1Ω = 12V 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 DRAIN-TO-SOURCE VOLTAGE ( 1Ω ...

Page 8

... Typical Performance Curves 0.65 HIP4020 SPLIT 5V COMMON GROUND 0.60 V SAT 0. 0. 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 0 FIGURE 8. TYPICAL CHARACTERISTIC OF SATURATION VOLTAGE vs OUTPUT CURRENT USING A +5V SUPPLY, T 0.70 HIP4020 SPLIT ±3V 0.65 V SAT 0. 0. 0.50 V SSA 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 0 FIGURE 9. TYPICAL CHARACTERISTIC OF SATURATION VOLTAGE vs OUTPUT CURRENT USING A ±3V SPLIT SUPPLY, OUTPUT REFERENCE EQUAL LOGIC GROUND, T ...

Page 9

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 HIP4020 M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE ...

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