W83977EF Winbond Electronics Corp America, W83977EF Datasheet
W83977EF
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W83977EF Summary of contents
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... W83977EF WINBOND I/O ...
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... W83977EF Data Sheet Revision History Pages Dates 1 n.a. 06/01/98 4,7,49,50,53,55, 2 06/16/98 90,91 3 n.a. 12/30/03 4 03/07/03 P86~P110 5 04/25/ Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS ...
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... ODE ARALLEL ORT 1.6 FDC I ............................................................................................................................ 16 NTERFACE 1.7 KBC I ............................................................................................................................ 18 NTERFACE 1.8 POWER PINS .............................................................................................................................. 18 1.9 ACPI I ........................................................................................................................... 18 NTERFACE 2.0 FDC FUNCTIONAL DESCRIPTION............................................................................................... 19 2.1 W83977EF FDC .......................................................................................................................... 19 2.1.1 AT interface ........................................................................................................................... 19 2.1.2 FIFO (Data) ........................................................................................................................... 19 2.1.3 Data Separator...................................................................................................................... 20 2.1.4 Write Precompensation......................................................................................................... 20 2.1.5 Perpendicular Recording Mode ............................................................................................ 21 2.1.5 Perpendicular Recording Mode ............................................................................................ 21 2.1.6 FDC Core .............................................................................................................................. 21 2.1.7 FDC Commands ................................................................................................................... 21 2 ............................................................................................................... 33 EGISTER ESCRIPTIONS 2 ...
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... KB Control Register (Logic Device 5, CR-F0) ................................................................. 74 6.5.2 Port 92 Control Register (Default Value = 0x24)............................................................. 74 6 ECURITY EYBOARD AND ............................................................................................................ 55 (EPP)................................................................................................. 56 (ECP) P ........................................................................... 61 ARALLEL ORT (EXTFDD) .......................................................................................... 69 (EXT2FDD) ...................................................................................... ESET ONTROL OGIC .............................................................. 75 OUSE AKE P -III - W83977EF ........................................................... 73 Publication Release Date: April 2003 Revision 1.1 ...
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... EPP Data or Address Write Cycle Timing Parameters.................................................... 125 11.3.6 Parallel Port FIFO Timing Parameters............................................................................. 126 11.3.7 ECP Parallel Port Forward Timing Parameters ............................................................... 126 11.3.8 ECP Parallel Port Reverse Timing Parameters ............................................................... 126 ....................................................................................................... 80 .......................................................................................................... 83 R ............................................................................................ 86 EGISTER P ) .......................................................................................... 96 ORT I) .......................................................................................... 101 ORT II) ......................................................................................... 105 ORT ................................................................................................... 117 -IV - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... APPLICATION CIRCUITS .......................................................................................................... 141 13 ARALLEL ORT XTENSION 13 ARALLEL ORT XTENSION 13.3 F FDD M ..................................................................................................................... 143 OUR ODE 14.0 ORDERING INFORMATION ...................................................................................................... 143 15.0 HOW TO READ THE TOP MARKING ...................................................................................... 143 16.0 PACKAGE DIMENSIONS.......................................................................................................... 144 .................................................................................................. 140 .................................................................................................... 140 - T ......................................................................................... 140 UP IMING FDD ............................................................................................. 141 2FDD ........................................................................................... 142 -V - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... TM Phoenix MultiKey/ customer code. The W83977EF provides a set of flexible I/O control functions to the system designer through a set of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured to provide a predefined alternate function. The W83977EF also supports Power-loss control, and makes the system never miss to detect any Wake-Up event provided by the chipset such as INTEL PIIX4 W83977EF is made to fully comply with Microsoft PC98 Hardware Design Guide ...
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... Support 3-mode FDD, and its Win95 driver UART • Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs • MIDI compatible • Fully programmable serial-interface characteristics: --- 8-bit characters --- Even, odd or no parity bit generation/detection --- 1, 1 stop bits generation Publication Release Date: April 2003 -2 - W83977EF Revision 1.1 ...
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... Support both interrupt and polling modes • Fast Gate A20 and Hardware Keyboard Reset • 8 Bit Timer/ Counter • Support binary and BCD arithmetic • 6MHz, 8 MHz, 12 MHz MHz operating frequency TM TM -2, Phoenix MultiKey/42 or customer code Publication Release Date: April 2003 -3 - W83977EF 16 -1) Revision 1.1 ...
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... General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, watching dog timer output, power LED output, infrared I/O pins, general purpose address decoder, KBC control I/O pins OnNow Funtions • Keyboard Wake-Up by programmable keys • Mouse Wake-Up by programmable buttons Package • 128-pin PQFP Publication Release Date: April 2003 -4 - W83977EF Revision 1.1 ...
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... W83977EF ...
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... CPU I/O read signal ts CPU I/O write signal ts System address bus enable ts In EPP Mode, this pin is the IO Channel Ready output to extend 24 the host read/write cycle. Master Reset; Active high low during normal operations W83977EF FUNCTION Publication Release Date: April 2003 Revision 1.1 ...
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... DMA Channel 3 request signal Terminal Count. When active, this pin indicates termination of a DMA transfer. Interrupt request 1 Interrupt request 3 Interrupt request 4 Interrupt request 5 Interrupt request 6 Interrupt request 7 Interrupt request 9 Interrupt request 10 Interrupt request 11 Interrupt request W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... Alternate Function from GP21: KBC P13 I/O port. KBC P16 I/O port. (CR2B bit 4_3 = 10) Panel Switch output. (CR2B bit default) General purpose I/O port 2 bit 2. (CR2B bit Alternate Function from GP22: KBC P14 I/O port W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... HEFRAS, which provides the power-on value for CR26 bit 6 (HEFRAS). A 4.7 k Ω is recommended if intends to pull up. (select 370H as configuration I/O port ′ s address) UART B Request To Send. An active low signal informs the modem or data set that the controller is ready to send data W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. FUNCTION Infrared Receiver input. Infrared Transmitter Output. -10 - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... ECP and EPP mode. EXTENSION FDD MODE: WD2# This pin is for Extension FDD B; its function is the same as the WD# pin of FDC. EXTENSION 2FDD MODE: WD2# This pin is for Extension FDD A and B; its function is the same as the WD# pin of FDC. -11 - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... EXTENSION FDD MODE: HEAD2# This pin is for Extension FDD B; its function is the same as the HEAD#pin of FDC. EXTENSION 2FDD MODE: HEAD2# This pin is for Extension FDD A and B; its function is the same as the HEAD# pin of FDC. -12 - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... EXTENSION FDD MODE: DRVDEN0 This pin is for Extension FDD B; its function is the same as the DRVDEN0 pin of FDC. EXTENSION 2FDD MODE: DRVDEN0 This pin is for Extension FDD A and B; its function is the same as the DRVDEN0 pin of FDC. -13 - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... This pin is for Extension FDD B; the function of this pin is the same as the WP# pin of FDC pulled high internally. EXTENSION. 2FDD MODE: WP2# This pin is for Extension FDD A and B; the function of this pin is the same as the WP# pin of FDC pulled high internally. -14 - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION. 2FDD MODE: MOA2# This pin is for Extension FDD A; its function is the same as the MOA# pin of FDC. -15 - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... Direction of the head step motor. An open drain output. Logic 1 = outward motion Logic 0 = inward motion Motor B On. When set to 0, this pin enables disk drive 1. This is an open drain output. -16 - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... This Schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. This input pin is pulled up internally Ω resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). -17 - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... W83C45 KINH (P17) Input. (CR2B bit default) General purpose I/O port 1 bit 3. (CR2B bit FUNCTION +5V power supply for the digital circuitry +5V stand-by power supply for the digital circuitry Ground FUNCTION battery voltage input 32.768Khz Clock Input 32.768Khz Clock Output -18 - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... FDC FUNCTIONAL DESCRIPTION 2.1 W83977EF FDC The floppy disk controller of the W83977EF integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible values. The FIFO provides better system performance in multi-master systems. The digital data separator supports bits/sec data rate ...
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... The FDC monitors the bit stream that is being sent to the drive. The data patterns that require precompensation are well known. Depending upon the pattern, the bit is shifted either early or late relative to the surrounding bits. Publication Release Date: April 2003 -20 - W83977EF Revision 1.1 ...
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... FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk. 2.1.6 FDC Core The W83977EF FDC is capable of performing twenty commands. Each command is initiated by a multi-byte transfer from the microprocessor. The result can also be a multi-byte transfer back to the microprocessor ...
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... RCN: Relative Cylinder Number R/W: Read/Write SC: Sector/per cylinder SK: Skip deleted data address mark SRT: Step Rate Time ST0: Status Register 0 ST1: Status Register 1 ST2: Status Register 2 ST3: Status Register 3 WG: Write gate alters timing of WE Publication Release Date: April 2003 -22 - W83977EF Revision 1.1 ...
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... N ------------------------ HDS DS1 DS0 -23 - W83977EF D1 D0 REMARKS 1 0 Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Publication Release Date: April 2003 ...
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... HDS DS1 DS0 -24 - W83977EF D0 REMARKS 0 Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Publication Release Date: April 2003 Revision 1.1 ...
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... HDS DS1 DS0 -25 - W83977EF REMARKS Command codes Sector ID information prior to command execution Data transfer between the FDD and system; FDD reads contents of all cylinders from index hole to EOT Status information after command execution Sector ID information after ...
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... HDS DS1 DS0 HDS DS1 DS0 -26 - W83977EF D0 REMARKS 0 Command codes The first correct ID information on the cylinder is stored in Data Register Status information after command execution Disk status after the command has been completed D0 REMARKS 0 Command codes ...
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... HDS DS1 DS0 -27 - W83977EF D0 REMARKS 0 Command code 0 Enhanced controller D0 REMARKS 1 Command codes Sector ID information prior to Command execution Data transfer between the FDD and system Status information after Command execution Sector ID information after Command execution Publication Release Date: April 2003 Revision 1 ...
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... HDS DS1 DS0 -28 - W83977EF D0 REMARKS 1 Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Publication Release Date: April 2003 Revision 1.1 ...
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... HDS DS1 DS0 DS1 DS0 -29 - W83977EF D0 REMARKS 1 Command codes Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters Status information after command execution D0 REMARKS 1 Command codes Head retracted to Track 0 Interrupt Publication Release Date: April 2003 ...
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... HDS DS1 DS0 -30 - W83977EF REMARKS Command code Status information at the end of each seek operation D0 REMARKS 1 Command codes REMARKS 1 Command codes Head positioned over proper cylinder on diskette D0 REMARKS 1 Configure information 0 Internal registers written Publication Release Date: April 2003 Revision 1 ...
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... GAP LOCK 0 0 -31 - W83977EF D0 REMARKS 1 Command codes D0 REMARKS 1 0 Registers placed in FIFO WG D0 REMARKS 0 Command Code D0 REMARKS 0 Command Code 0 0 Publication Release Date: April 2003 Revision 1.1 ...
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... ST0 ---------------------- HDS DS1 DS0 -32 - W83977EF D0 REMARKS 0 Command Code Status information about disk drive D0 REMARKS Invalid codes (no operation- FDC goes to standby state) ST0 = 80H Publication Release Date: April 2003 Revision 1.1 ...
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... Register Descriptions There are several status, data, and control registers in W83977EF. These registers are defined below: ADDRESS OFFSET base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 base address + 5 base address + 7 2.2.1 Status Register A (SA Register) (Read base address + 0) This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 ...
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... This bit indicates the value of HEAD# output. 0 side 1 1 side 0 INDEX (Bit 2): This bit indicates the complement of INDEX# output. WP (Bit 1): 0 disk is not write-protected DIR# WP INDEX HEAD# TRAK0 STEP F/F DRQ INIT PENDING -34 - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... MOT EN A (Bit 0) This bit indicates the complement of the MOA# output pin. In PS/2 Model 30 mode, the bit definitions for this register are as follows -35 - W83977EF MOT EN A MOT RDATA Toggle WDATA Toggle Drive SEL0 Publication Release Date: April 2003 Revision 1.1 ...
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... This bit indicates the complement of latched WE# output pin. DSD# (Bit 1): 0 Drive D has been selected 1 Drive D has not been selected DSC# (Bit 0): 0 Drive C has been selected 1 Drive C has not been selected DSC# DSD# WE F/F RDATA F/F WD F/F DSA# DSB# DRV2# -36 - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... -37 - W83977EF 01 select drive B 10 select drive C 11 select drive D Tape sel 0 Tape sel 1 Tape Sel 0 Tape Sel 1 Floppy boot drive 0 Floppy boot drive 1 Drive type ID0 Drive type ID1 Media ID0 Media ID1 Publication Release Date: April 2003 ...
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... DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor. If DIO = LOW then transfer is from processor to Data Register. Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor. -38 - W83977EF None Publication Release Date: April 2003 Revision 1 ...
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... POWER DOWN S/W RESET PRECOMPENSATION DELAY 250K - 1 Mbps Default Delays 41.67 nS 83.34 nS 125.00 nS 166.67 nS 208.33 nS 250.00 nS 0.00 nS (disabled) DEFAULT PRECOMPENSATION DELAYS 125 nS 125 nS 125 nS 41.67nS 20.8 nS -39 - W83977EF 2 Mbps Tape drive Default Delays 20.8 nS 41.17 nS 62.5nS 83.3 nS 104.2 nS 125.00 nS 0.00 nS (disabled) Publication Release Date: April 2003 Revision 1.1 ...
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... This register stores data, commands, and parameters and provides diskette-drive status information. Data bytes are passed through the data register to program or obtain results after a command. In the W83977EF, this register defaults to FIFO disabled mode after reset. The FIFO can change its value and enable its operation through the CONFIGURE command. ...
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... During execution of the read data or scan command 0 No error Not used. This bit is always -41 - W83977EF US0 Unit Select 0 US1 Unit Select 1 HD Head Address TS Two-Side TO Track 0 RY Ready WP Write Protected FT Fault Publication Release Date: April 2003 Revision 1.1 ...
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... KB MB/S data rate (high density FDD) 1 250 KB/S or 300 KB/S data rate Reserved for the hard disk controller During a read of this register, these bits are in tri-stat DSKCHG HIGH DENS# DRATE0 DRATE1 DSKCHG -42 - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... These two bits select the data rate of the FDC. In the PS/2 Model 30 mode, the bit definitions are as follows -43 - W83977EF DRATE0 DRATE1 NOPREC DMAEN DSKCHG# 0 DRATE0 DRATE1 Publication Release Date: April 2003 Revision 1.1 ...
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... NOPREC (Bit 2): This bit indicates no precompensation. It has no function and can be set by software. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC Reserved -44 - W83977EF DRATE0 DRATE1 NOPREC Publication Release Date: April 2003 Revision 1.1 ...
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... Data length select bit 1(DLS1) Multiple stop bits enable (MSBE) Parity bit enable (PBE) Even parity enable (EPE) Parity bit fixed enable (PBFE) Set silence enable (SSE) Baudrate divisor latch access bit (BDLAB) Bit Number -45 - W83977EF Publication Release Date: April 2003 Revision 1 ...
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... CTS DSR RI Falling Toggling Toggling Edge (TCTS) (TDSR) (FERI) Bit 0 Bit 1 Bit 2 Bit 0 Bit 1 Bit 2 Bit 8 Bit 9 Bit 10 -46 - W83977EF RX Data RX Data RX Data Bit 3 Bit 4 Bit 5 TX Data TX Data TX Data Bit 3 Bit 4 Bit 5 HSR 0 0 Interrupt Enable (EHSRI) Interrupt 0 ...
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... Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in each serial character. TABLE 3-2 WORD LENGTH DEFINITION DLS1 DLS0 DATA LENGTH 5 bits 6 bits 7 bits 8 bits -47 - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE) Transmitter Shift Register empty (TSRE) RX FIFO Error Indication (RFEI) -48 - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... Loopback RI input IRQ enable Internal loopback enable CTS# toggling (TCTS) DSR# toggling (TDSR) RI falling edge (FERI) DCD# toggling (TDCD) Clear to send (CTS) Data set ready (DSR) Ring indicator (RI) Data carrier detect (DCD) -49 - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... FIFO enable Receiver FIFO reset Transmitter FIFO reset DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB -50 - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... RBR data ready 2. FIFO interrupt active level reached FIFO Data Timeout Data present in RX FIFO for 4 characters period of time since last access of RX FIFO. -51 - W83977EF 0 if interrupt pending Interrupt Status bit 0 Interrupt Status bit 1 Interrupt Status bit 2 FIFOs enabled FIFOs enabled Clear Interrupt - 2 ...
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... TBR empty interrupt enable (ETBREI) UART receive status interrupt enable (EUSRI) Handshake status interrupt enable (EHSRI) Pre-Div: 1.0 Decimal divisor used to generate 16X 24M Hz clock -52 - W83977EF 1. Write data into TBR 2. Read ISR (if priority is third) 2. TDSR = 1 Read HSR 4. TDCD = 1 16 -1. The output frequency of ...
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... Note. Pre-Divisor is determined by CRF0 of UART A and B. 650 2304 975 1536 1430 1047 1478.5 857 1950 768 3900 384 7800 192 15600 96 23400 64 26000 58 31200 48 46800 32 62400 24 93600 16 124800 12 249600 6 499200 3 748800 2 1497600 1 -53 - W83977EF ** ** 0.18% 0.099 0.53 Publication Release Date: April 2003 Revision 1.1 ...
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... IR PORT The Infrared (IR) function provides point-to-point (or multi-point to multi-point) wireless communication which can operate under various transmission protocols including IrDA 1.0 SIR, SHARP ASK-IR. IR port shares the same port with UART B port in W83977EF. configuration information. Please refer to section 11.5 for Publication Release Date: April 2003 ...
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... PARALLEL PORT 5.1 Printer Interface Logic The parallel port of the W83977EF makes possible the attachment of various devices that accept eight bits of parallel data at standard TTL level. The W83977EF supports an IBM XT/AT compatible parallel port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended Capabilities Parallel Port (ECP), Extension FDD mode (EXTFDD), Extension 2FDD mode (EXT2FDD) on the parallel port ...
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... Printer status buffer (Read) 0 Printer control latch (Write) 0 Printer control swapper (Read) 1 EPP address port (R/W) 0 EPP data port 0 (R/W) 1 EPP data port 1 (R/W) 0 EPP data port 2 (R/W) 1 EPP data port 2 (R/W) -56 - W83977EF EXT2FDD PIN EXTFDD ATTRIBUTE --- --- --- INDEX2# I INDEX2# TRAK02# I TRAK02# WP2# I ...
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... Writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0 has no effect ACK# BUSY# stops. -57 - W83977EF TMOUT ERROR# SLCT PE ACK# BUSY# signal means the printer has Publication Release Date: April 2003 Revision 1.1 ...
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... The address port is available only in EPP mode. Bit definitions are as follows STROBE AUTO FD INIT# SLCT IN IRQ ENABLE DIR ACK -58 - W83977EF changes from low to high. 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Publication Release Date: April 2003 Revision 1.1 ...
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... PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 -59 - W83977EF PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 IOR# causes an EPP read PD2 PD1 PD0 1 1 TMOUT INIT# AUTOFD# ...
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... The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive high. EPP DESCRIPTION WAIT# is deasserted. The current EPP cycle is Publication Release Date: April 2003 -60 - W83977EF Revision 1.1 ...
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... ECP FIFO (Address) R All Status Register R/W All Control Register R/W 010 Parallel Port Data FIFO R/W 011 ECP FIFO (DATA) R/W 110 Test FIFO R 111 Configuration Register A R/W 111 Configuration Register B R/W All Extended Control Register DESCRIPTION Publication Release Date: April 2003 -61 - W83977EF FUNCTION Revision 1.1 ...
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... These bits are at low level during a read of the Printer Status Register. The bits of this status register are defined as follows -62 - W83977EF 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Address or RLE Address/RLE 1 nFault Select PError nAck nBusy Publication Release Date: April 2003 Revision 1.1 ...
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... Bit 2: This bit is output to the Bit 1: This bit is inverted and output to the Bit 0: This bit is inverted and output to the output. AFD# output. STB# output. -63 - W83977EF strobe autofd nInit SelectIn ackIntEn Direction ACK# input. Publication Release Date: April 2003 Revision 1.1 ...
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... Bit 7: This bit is read-only low level during a read. This means that this chip does not support hardware RLE compression. Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts -64 - W83977EF IRQx 0 IRQx 1 IRQx 2 intrValue compress Publication Release Date: April 2003 Revision 1.1 ...
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... Configuration Mode. The confgA and confgB registers are accessible at 0x400 and 0x401 in this mode. Bit 4: Read/Write (Valid only in ECP Mode) IRQ resource -65 - W83977EF . empty full service Intr dmaEn nErrIntrEn MODE MODE MODE Publication Release Date: April 2003 Revision 1.1 ...
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... These registers are available in all modes. 2. All FIFOs use one common 16-byte FIFO PD5 PD4 PD3 PError Select nFault Directio ackIntEn SelectIn nErrIntrEn dmaEn serviceIntr -66 - W83977EF NOTE PD2 PD1 PD0 nInit autofd strobe ...
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... ECP Mode. This signal sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. This signal is always deasserted in ECP mode. -67 - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... PeriphAck is low. The most significant bit of the command is always zero. 5.3.13.3 Data Compression The W83977EF supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported. In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo ...
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... I/O will empty or fill the FIFO using the appropriate direction and mode. 5.4 Extension FDD Mode (EXTFDD) In this mode, the W83977EF changes the printer interface pins to FDC input/output pins, allowing the user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin assignments for the FDC input/output pins are shown in Table 5-1. ...
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... KEYBOARD CONTROLLER The KBC (8042 with licensed KB BIOS) circuit of W83977EF is designed to provide the functions needed to interface a CPU with a keyboard and/or a PS/2 mouse, and can be used with IBM compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer ...
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... Data byte 1: Command byte 0: Keyboard is inhibited 1: Keyboard is not inhibited 0: Auxiliary device output buffer empty 1: Auxiliary device output buffer full 0: No time-out error 1: Time-out error 0: Odd parity 1: Even parity (error) Publication Release Date: April 2003 -71 - W83977EF Revision 1.1 ...
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... Enable Keyboard Interrupt BIT BIT DEFINITION No Error Detected 00 01 Auxiliary Device "Clock" line is stuck low Auxiliary Device "Clock" line is stuck high 02 03 Auxiliary Device "Data" line is stuck low 04 Auxiliary Device "Data" line is stuck low -72 - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... The KBC implements a hardware control logic to speed-up GATEA20 and KBRESET. This control logic is controlled by LD5-CRF0 as follows: FUNCTION BIT BIT DEFINITION No Error Detected 00 01 Keyboard "Clock" line is stuck low 02 Keyboard "Clock" line is stuck high Keyboard "Data" line is stuck low 03 04 Keyboard "Data" line is stuck high -73 - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... A "1" on this bit causes KBRESET to drive low for 6 µ S(Min.) with 14 µ S(Min.) delay. Before issuing another keyboard reset command, the bit must be cleared Res. (1) Res. (0) Res. (0) -74 - W83977EF P92EN HGA20 HKBRST Res. (1) SGA20 PLKBRST Publication Release Date: April 2003 Revision 1 ...
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... The bit 4 of LD-0A CR-E0 determines which button (left or right) to perform Wake-Up function. TM chipset TX, LX PIIX4) panel switch input. The Wake-Up pin must be connected to + BAT Publication Release Date: April 2003 -75 - W83977EF of ATX SB pin to store the data (the Revision 1.1 ...
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... General Purpose I/O W83977EF provides 14 Input/Output ports that can be individually configured to perform a simple basic I/O function or a pre-defined alternate function. Those 14 GP I/O ports are divided into three groups, the first group contains 8 ports, and the second group contains only 6 ports. Each port in first group corresponds to a configuration register in logical device 7, and the second group in logical device 8 ...
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... Figure 7.2 Figure 7.3 Publication Release Date: April 2003 -77 - W83977EF Revision 1.1 ...
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... Basic I/O functions The Basic I/O functions of W83977EF provide several I/O operations including driving a logic value to output port, latching a logic value from input port, inverting the input/output logic value, and steering Common Interrupt (only available in the second group of the GP I/O port). Common Interrupt is the ORed function of all interrupt channels in the second group of the GP I/O ports, and it also connects to a 1ms debounce filter which can reject a noise pulse width or less ...
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... GP1 GP2 REGISTER BIT GP I/O PORT ASSIGNMENT BIT 0 GP10 BIT 1 GP11 BIT 2 GP12 BIT 3 GP13 BIT 4 GP14 BIT 5 GP15 BIT 6 GP16 BIT 7 GP17 BIT 0 GP20 BIT 1 GP21 BIT 2 GP22 BIT 3 GP23 BIT 4 GP24 BIT 5 GP25 -79 - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... Alternate I/O Functions W83977EF provides several alternate functions which are scattered among the GP I/O ports. Table 7.2.1 shows their assignments. Polarity bit can also be set to alter their polarity. Table 7.2.1 GP I/O PORT GP10 Interrupt Steering GP11 Interrupt Steering GP12 Watch Dog Timer Output/IRRX input GP13 Power LED output/IRTX output ...
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... Users can alter its polarity through the polarity bit of the GP14 and GP15 configuration register. WDT_CTRL1 BIT[ -81 - W83977EF POWER LED STATE Toggle pulse Continuous high or low * Continuous high or low * Toggle pulse Publication Release Date: April 2003 Revision 1.1 ...
Page 88
... Plug and Play Configuration The W83977EF uses Compatible PNP protocol to access configuration registers for setting up different types of configurations. In W83977EF, there are nine Logical Devices (from Logical Device 0 to Logical Device A with the exception of logical device 4 and 6 for compatibility) which correspond to nine individual functions: FDC (logical device 0), PRT (logical device 1), UART1 (logical device 2), UART2 (logical device 3), KBC (logical device 5), GPIO1 (logical device 7), GPIO2 (logical device 8), and ACPI ((logical device A) ...
Page 89
... Extended Functions Enable Registers (EFERs) After a power-on reset, the W83977EF enters the default operating mode. Before the W83977EF enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers ...
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... MOV DX,3F1H MOV AL,01H OUT DX,AL ; select logical device 1 ; MOV DX,3F0H MOV AL,F0H OUT DX,AL ; select CRF0 MOV DX,3F1H MOV AL,3CH OUT DX,AL ; update CRF0 with value 3CH ;------------------------------------------ ; Exit extended function mode ;------------------------------------------ MOV DX,3F0H MOV AL,AAH OUT DX,AL | -84 - W83977EF | Publication Release Date: April 2003 Revision 1.1 ...
Page 91
... ACPI Registers Features W83977EF supports both ACPI and legacy power managements. The switch logic of the power management block generates an SMI# interrupt in the legacy mode and an SCI# interrupt in the ACPI mode. The new ACPI feature routes SMI#/SCI# logic output either to SMI# or toSCI#. The SMI#/SCI# logic routes to SMI# only when both SCI_EN = 0 and SMISCI_OE = 1 ...
Page 92
... Bit 2, 1: Reserved. Bit 0: FDCPWD = 0 Power down = 1 No Power down CR23 (Default 0xFE) Bit Reserved. Bit 0: IPD (Immediate Power Down). When set will put the whole chip into power down mode immediately. Publication Release Date: April 2003 -86 - W83977EF Revision 1.1 ...
Page 93
... PnP registers if the present value of PNPCSV The corresponding power-on setting pin is NDTRA (pin 44). CR25 (Default 0x00) Bit Reserved Bit 5: URBTRI Bit 4: URATRI Bit 3: PRTTRI Bit Reserved Bit 0: FDCTRI. Publication Release Date: April 2003 -87 - W83977EF Revision 1.1 ...
Page 94
... Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ Bit 0: DSUBLGRQ = 0 Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ = 1 Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ Publication Release Date: April 2003 -88 - W83977EF Revision 1.1 ...
Page 95
... Bit 7: PIN57S = 0 KBRST = 1 GP12 Bit 6: PIN56S = 0 GA20 = 1 GP11 Bit PIN40S1, PIN40S0 = 00 CIRRX = 01 GP24 = 10 8042 P13 = 11 Reserved Bit PIN39S1, PIN39S0 = 00 SUSCIN Reserved = 10 GP25 = 11 Reserved Bit PIN3S1, PIN3S0 = 00 DRVDEN1 = 01 GP10 = 10 8042 P12 = 11 SCI# Publication Release Date: April 2003 -89 - W83977EF Revision 1.1 ...
Page 96
... GP20 = 10 Reserved = 11 Reserved Bit 0: PIN58S = 0 KBLOCK = 1 GP13 CR2C (Default 0x00) Bit PIN121S1, PIN121S0 = 00 DRQ0 = 01 GP17 = 10 8042 P14 = 11 SCI# Bit PIN119S1, PIN119S0 = 00 NDACK0 = 01 GP16 = 10 8042 P15 = 11 Reserved Bit PIN104S1, PIN104S0 = 00 IRQ15 Publication Release Date: April 2003 -90 - W83977EF Revision 1.1 ...
Page 97
... Reserved Bit PIN103S1, PIN103S0 = 00 IRQ14 = 01 GP14 = 10 PLEDO = 11 Reserved CR2D (Default 0x00) Test Modes: Reserved for Winbond. CR2E (Default 0x00) Test Modes: Reserved for Winbond. CR2F (Default 0x00) Test Modes: Reserved for Winbond. Publication Release Date: April 2003 -91 - W83977EF Revision 1.1 ...
Page 98
... Bit 5: DRV2EN (PS2 mode only) When this bit is a logic 0, this indicates that a second drive is installed and is reflected in status register A. Bit 4: Swap Drive 0, 1 Mode = 0 No Swap (Default Drive and Motor sel 0 and 1 are swapped. Publication Release Date: April 2003 -92 - W83977EF Revision 1.1 ...
Page 99
... Normal = Forced to logic Forced to logic 0) Bit 1: DISFDDWR = 0 Enable FDD write Disable FDD write(forces pins WE, WD stay high). Bit 0: SWWP = 0 Normal, use WP to determine whether the FDD is write protected or not FDD is always write-protected. Publication Release Date: April 2003 -93 - W83977EF Revision 1.1 ...
Page 100
... Select Regular drives and 2.88 format = 01 Specifical application = 10 2 Meg Tape = 11 Reserved Bit 2: Reserved. Bit 1:0: DMOD0, DMOD1 : Drive Model select (Refer to TABLE B). DRATE1 DRATE0 SELDEN -94 - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
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... DRVDEN1(pin 3) SELDEN DRATE0 DRATE1 DRATE0 DRATE0 SELDEN DRATE0 DRATE1 -95 - W83977EF SELDEN FM CRF0 bit 0=0 --- 1 250K 1 150K 0 125K 0 --- 1 250K 1 250K 0 125K 0 --- 1 250K 1 --- 0 125K 0 DRIVE TYPE 4/2/1 MB 3.5”“ ...
Page 102
... EPP - 1.9 and SPP mode = 101 EPP - 1.7 and SPP mode = 010 ECP mode = 011 ECP and EPP - 1.9 mode = 111 ECP and EPP - 1.7 mode. 10.4 Logical Device 2 (UART A)¢) CR30 (Default 0x01 if PNPCSV during POR, default 0x00 otherwise) Publication Release Date: April 2003 -96 - W83977EF Revision 1.1 ...
Page 103
... CR60 (Default 0x02, 0xF8 if PNPCSV during POR, default 0x00, 0x00 otherwise) These two registers select Serial Port 2 I/O base address [0x100:0xFF8 byte boundary. CR70 (Default 0x03 if PNPCSV during POR, default 0x00 otherwise) Bit Reserved. Bit [3:0]: These bits select IRQ resource for Serial Port 2. Publication Release Date: April 2003 -97 - W83977EF Revision 1.1 ...
Page 104
... Active pulse 1.6 µ S Active pulse 3/16 bit time Inverting IRTX/SOUTB pin Inverting IRTX/SOUTB & 500 KHZ clock Inverting IRTX/SOUTB Inverting IRTX/SOUTB & 500 KHZ clock -98 - W83977EF IRRX high Demodulation into SINB/IRRX Demodulation into SINB/IRRX routed to SINB/IRRX routed to SINB/IRRX Demodulation into SINB/IRRX Demodulation into SINB/IRRX Publication Release Date: April 2003 Revision 1 ...
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... SOUTB pin of UART B function or IRTX pin of IR function. Bit 0: RX2INV the SINB pin of UART B function or IRRX pin of IR function in normal condition inverse the SINB pin of UART B function or IRRX pin of IR function Publication Release Date: April 2003 -99 - W83977EF Revision 1.1 ...
Page 106
... Select 12Mhz as KBC clock input Select 16Mhz as KBC clock input. Bit Reserved. Bit Port 92 disable Port 92 enable. Bit Gate20 software control Gate20 hardware speed up. Bit KBRST software control KBRST hardware speed up. Publication Release Date: April 2003 -100 - W83977EF Revision 1.1 ...
Page 107
... CRE0 (GP10, Default 0x01) Bit Reserved. Bit 4: IRQ Filter Select = 1 Debounce Filter Enabled = 0 Debounce Filter Bypassed Bit 3: Select Function Select Alternate Function: Interrupt Steering Select Basic I/O Function. Bit 2: Reserved. Bit 1: Polarity Invert Invert. Publication Release Date: April 2003 -101 - W83977EF Revision 1.1 ...
Page 108
... Bit 4: IRQ Filter Select = 1 Debounce Filter Enabled = 0 Debounce Filter Bypassed Bit 3: Select Function Select Alternate Function: Interrupt Steering Select Basic I/O Function. Bit 2: Reserved. Bit 1: Polarity Invert Invert. Bit 0: In/Out selection Input Output. Publication Release Date: April 2003 -102 - W83977EF Revision 1.1 ...
Page 109
... Bit Decode two byte address Select 2nd alternate function: Keyboard Inhibit(P17 Reserved Bit 2: Reserved. Bit 1: Polarity: 1: Invert Invert Bit 0: In/Out: 1: Input, 0: Output CRE5 (GP15, Default 0x01) Bit Address decoder is 1-Byte boundary. Publication Release Date: April 2003 -103 - W83977EF Revision 1.1 ...
Page 110
... Select 1st alternate function: Power LED output. Please refer to TABLE Reserved Bit 2: Reserved. Bit 1: Polarity: 1: Invert Invert Bit 0: In/Out: 1: Input, 0: Output TABLE C WDT_CTRL1* BIT[1 WDT_CTRL0* BIT[3] WDT_CTRL1 BIT[ -104 - W83977EF POWER LED STATE X 1 Hertz Toggle pulse X Continuous high or low* Publication Release Date: April 2003 Revision 1.1 ...
Page 111
... Bit These bits select IRQ resource for Watch Dog. CRE8 (GP20, Default 0x01) Bit Reserved. Bit Select Function Select basic I/O function = 01 Reserved = 10 Select alternate function: Keyboard Reset (connected to KBC P20 Publication Release Date: April 2003 -105 - W83977EF Continuous high or low* 1 Hertz Toggle pulse Revision 1.1 ...
Page 112
... CREB (GP23, Default 0x01) Bit Reserved. Bit Select Function Select Basic I/O function = 01 Reserved = 10 Select 2nd alternate function: Keyboard P15 I Reserved Bit 2: Int Enable Common IRQ = 0 Disable Common IRQ Bit 1: Polarity: 1: Invert Invert Publication Release Date: April 2003 -106 - W83977EF Revision 1.1 ...
Page 113
... Interrupt or Keyboard Interrupt happen will also cause to reload the non-zero value to Watch Dog Counter and count down. Read this register can not access Watch Dog Timer Time-out value, but can access the current value in Watch Dog Counter. Publication Release Date: April 2003 -107 - W83977EF Revision 1.1 ...
Page 114
... Time-out occurs after 255 minutes CRF3 (WDT_CTRL0, Default 0x00) Watch Dog Timer Control Register #0 Bit Reserved Bit 3: When Time-out occurs, Enable or Disable Power LED with 1 Hz and 50% duty cycle output Enable = 0 Disable Publication Release Date: April 2003 -108 - W83977EF Revision 1.1 ...
Page 115
... Internal logic provides an 1us Debounce Filter to reject the width of P20 pulse less than 1us. 2). The P20 signal that coming from Debounce Filter is ORed with the signal generated by the Force Time-out bit and then connect to set the Bit 0(Watch Dog Timer Status ORed signal is self-clearing. Publication Release Date: April 2003 -109 - W83977EF Revision 1.1 ...
Page 116
... CRE1 (Default 0x00) Keyboard Wake-Up Index Register This register is used to indicate which Keyboard Wake-Up Shift register or Predetermined key Register read/written via CRE2. The range of Keyboard Wake-Up index register is 0x00 - 0x0E, CRE2 Keyboard Wake-Up Data Register Publication Release Date: April 2003 -110 - W83977EF Revision 1.1 ...
Page 117
... Bit 1-0: Reserved. CRE5 (Default 0x00) Bit 7: Reserved. Bit Compared Code Length. When the compared codes are storaged in the data register, these data length should be written to this register. CRE6 (Default 0x00) Bit Reserved. Publication Release Date: April 2003 -111 - W83977EF Revision 1.1 ...
Page 118
... Bit 1: URAPME. UART A auto power management enable disable the auto power management functions enable the auto power management functions. Bit 0: URBPME. UART B auto power management enable disable the auto power management functions enable the auto power management functions. Publication Release Date: April 2003 -112 - W83977EF Revision 1.1 ...
Page 119
... UART A is now in the working state due to any UART A access, any IRQ, the receiver begins receiving a start bit, the transmitter shift register begins transmitting a start bit, and any transition on MODEM control input lines. start bit, and any transition on MODEM control input lines. Publication Release Date: April 2003 -113 - W83977EF Revision 1.1 ...
Page 120
... SMI#/SCI# interrupt due to UART C's IRQ enable the generation of an SMI#/SCI# interrupt due to UART C's IRQ. start bit, and any transition on MODEM control input lines. (GP10IRQEN and GP10IRQSTS) -114 - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
Page 121
... SMI#/SCI# interrupt due to common IRQ function's IRQ. Bit 1: GP11IRQEN disable the generation of an SMI#/SCI# interrupt due to GP11 interrupt steering's IRQ enable the generation of an SMI#/SCI# interrupt due to GP11 interrupt steering's IRQ. Publication Release Date: April 2003 -115 - W83977EF Revision 1.1 ...
Page 122
... Bit 0: SMISCI_OE: This is the SMI# and SCI# enable bit neither SMI# nor SCI# will be generated. Only the IRQ status bit is set SMI# or SCI# event will be generated. CRFE, FF (Default 0x00) Reserved for Winbond test. Publication Release Date: April 2003 -116 - W83977EF Revision 1.1 ...
Page 123
... +10 LIH I -10 LIL +10 LIH I -10 LIL -117 - W83977EF UNIT V +0 ° C ° C UNIT CONDITIONS 2.5 V BAT 5.0 V, All ACPI pins are SB not connected µ µ ...
Page 124
... LIL MIN. TYP. MAX. 0.3xV DD 0.7xV DD 0.4 3 0.3xV DD 0.7xV DD 0.4 3 0.3xV DD 0.7xV DD 0.4 3 0.3xV DD 0.7xV DD 0.4 3 -118 - W83977EF UNIT CONDITIONS µ µ µ µ ...
Page 125
... Input High Voltage V IH Input High Leakage I LIH Input Low Leakage I LIL MIN. TYP. MAX. 0.8 2.0 0.4 2 0.8 2.0 0.4 2 0.4 2.4 0.4 2.4 0.4 0.4 0.8 2.0 +10 -10 -119 - W83977EF UNIT CONDITIONS µ µ µ ...
Page 126
... LIH I LIL V 0.5 0 1.6 2 0.5 1 LIH I LIL V 0.5 0 1.6 2 0.5 1 LIH I LIL -120 - W83977EF MAX. UNIT CONDITIONS +10 µ -10 µ 1 3 µ -10 µ A ...
Page 127
... CL = 100 MCY 260/430 AA /510 -121 - W83977EF TYP. MAX. (NOTE 360/570 /675 360/570 /675 Publication Release Date: April 2003 Revision 1.1 UNIT ...
Page 128
... CONDITIONS T MRW T 135/220 TC T 1.8/3/3. RST T 0.5/0.9 IDX T 1.0/1.6 DST T 24/40/4 STD T 6.8/11.5 STP T Note 100/185 WDD T 100/138 WPC -122 - W83977EF TYP. MAX. (NOTE 1) 6/12 /20/24 /260 5 /1.0 /2.0 8 7/11.7 7.2/11.9 /13.8 /14 /14.2 Note 2 Note 2 125/210 150/235 /225 /250 /275 125/210 150/235 /225 /250 /275 Publication Release Date: April 2003 Revision 1.1 UNIT µ ...
Page 129
... IR T 100 pF Loading MWO T SIM T RIM T 100 pF Loading IAD T 100 pF Loading IID N 100 pF Loading SYM. MIN 200 t5 Publication Release Date: April 2003 -123 - W83977EF MIN. MAX. UNIT 9/16 Baud Rate 1 µ S 1/16 8/16 Baud Rate 175 nS 9/16 16/16 Baud Rate 1/2 Baud Rate 250 nS 200 nS ...
Page 130
... Publication Release Date: April 2003 -124 - W83977EF MAX. UNIT µ 160 185 nS 190 180 190 ...
Page 131
... Publication Release Date: April 2003 -125 - W83977EF MAX. UNIT 160 185 nS 185 210 nS 190 nS 10 µ S µ S ...
Page 132
... SYMBOL MIN Publication Release Date: April 2003 -126 - W83977EF MAX. UNIT 500 nS MAX. UNIT 180 nS 180 nS nS 200 nS nS 180 nS MAX. UNIT ...
Page 133
... MIN 100 Publication Release Date: April 2003 -127 - W83977EF MAX. UNIT µ µ S µ S µ S µ S µ µ µ S ...
Page 134
... SYMBOL t PANSWIN# falling edge to PANSWOUT# falling edge SWL t PANSWIN# falling edge to PANSWOUT# Hi-Z SWH t KCLK/MCLK falling edge to PANSWOUT# falling WKUPD edge delay t PANSWOUT# active pulse width WKUPW PARAMETER PARAMETER -128 - W83977EF MIN. MAX. UNIT 300(Note 1) ns MIN. MAX. UNIT 200 ns 0.5 1 ...
Page 135
... TRA TRR TDH TDF TR Processor Write Operation TWA TWW TWD TDW TWI DMA Operation DIR# TMCY TAA TMRW STEP -129 - W83977EF Write Date WD# TWDD Index INDEX# TIDX TIDX Terminal Count TC TTC Reset RESET TRST Drive Seek operation TSTP TDST TSTD TSC Publication Release Date: April 2003 Revision 1 ...
Page 136
... SERIAL OUT (SOUT) THRS IRQ3 or IRQ4 THR IOW (WRITE THR) IOR (READ TIR) Receiver Timing STAR DATA BITS (5-8) Transmitter Timing STAR DATA (5-8) PARITY THR TSI -130 - W83977EF PARITY STOP TSINT TRINT STAR STOP (1-2) TSTI TIR Publication Release Date: April 2003 Revision 1.1 ...
Page 137
... TRIM │ │ │ │ Printer Interrupt Timing ← TLAD │ │ │ │ │ -131 - W83977EF │ │ │ → ← TMWO │ │ │ │ │ TSIM │ │ │ │ → ← │ ...
Page 138
... Parallel Port 12.3.1 Parallel Port Timing IOW# INIT#, STROBE# AUTOFD, SLCTIN# PD<0:7> ACK# IRQ (SPP) IRQ (EPP or ECP) nFAULT (ECP) ERROR# (ECP) IRQ Publication Release Date: April 2003 -132 - W83977EF t3 t4 Revision 1.1 ...
Page 139
... EPP Data or Address Read Cycle (EPP Version 1.9) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE# t16 t17 PD<0:7> t21 t22 t23 t24 ADDRSTB DATASTB WAIT t18 t25 t27 t26 Publication Release Date: April 2003 -133 - W83977EF t4 t15 t19 t20 t28 Revision 1.1 ...
Page 140
... EPP Data or Address Write Cycle (EPP Version 1.9) A10-A0 SD<0:7> t1 IOW# IOCHRDY WRITE# PD<0:7> DATAST# ADDRSTB# WAIT# t22 PBDIR t10 t11 t13 t15 t16 t17 t19 t20 -134 - W83977EF t12 t14 t18 t21 Publication Release Date: April 2003 Revision 1.1 ...
Page 141
... EPP Data or Address Read Cycle (EPP Version 1.7) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE# t16 t17 PD<0:7> t21 t22 t23 ADDRSTB t24 DATASTB WAIT t18 t25 t26 t27 Publication Release Date: April 2003 -135 - W83977EF t4 t15 t19 t20 t28 Revision 1.1 ...
Page 142
... SD<0:7> t1 IOW# IOCHRDY WRITE# PD<0:7> DATAST# ADDRSTB# WAIT# 12.3.6 Parallel Port FIFO Timing PD<0:7> nSTROBE BUSY t10 t11 t13 t15 t16 t17 t19 t20 t1 t2 >| t6 >| -136 - W83977EF t22 t22 t18 t4 >| t3 >| t5 > >| Publication Release Date: April 2003 Revision 1.1 ...
Page 143
... ECP Parallel Port Forward Timing nAUTOFD PD<0:7> nSTROBE BUSY 12.3.8 ECP Parallel Port Reverse Timing PD<0:7> nACK nAUTOFD -137 - W83977EF Publication Release Date: April 2003 Revision 1.1 ...
Page 144
... Send Data to K/B CLOCK (KCLK) T12 SERIAL DATA START (KDAT) 12.4.4 Receive Data from K ACTIVE T7 DATA ACTIVE T10 T11 DATA OUT T14 T13 T19 -138 - W83977EF T17 T18 T16 D7 P STOP Publication Release Date: April 2003 Revision 1.1 ...
Page 145
... Receive Data from Mouse MCLK T29 MDAT START D0 T14 T13 T23 T24 T22 T26 T27 T28 -139 - W83977EF D7 P STOP D7 P STOP Bit D7 P STOP Bit Publication Release Date: April 2003 Revision 1.1 ...
Page 146
... GPIO Write Timing Diagram A0-A15 IOW# D0-7 GPIO10-17 GPIO20-25 12.6 Master Reset (MR) Timing Vcc MR 12.7 Keyboard/Mouse Wake-up Timing KCLK MCLK PANSWIN# PANSWOUT# HI-Z tSWL VALID VALID PREVIOUS STATE tVMR tWKUPD tSWZ -140 - W83977EF VALID tWGO tWKUPW Publication Release Date: April 2003 Revision 1.1 ...
Page 147
... STEP2#/SLIN# 4 WP2#/PD2 16 DIR2#/INIT# 3 TRK02#/PD1 15 HEAD2#/ERR# 2 IDX2#/PD0 14 RWC2#/AFD# 1 STB# PRINTER PORT Parallel Port Extension FDD Mode Connection Diagram JP13 -141 - W83977EF JP 13A DCH2 HEAD2 RDD2 WP2 TRK02 WE2 WD2# ...
Page 148
... D IR 2#/IN IT K02#/ EAD2#/ IDX2#/ 2#/AFD # 1 STB TER Parallel Port Extension 2FD D C onnection D iagram JP13 -142 - W83977EF JP 13A K02 ...
Page 149
... W83977EF-AW AM. MEGA. 87-96 821A2B282012345 1st line: Winbond logo 2nd line: the type number: W83977EF-AW 3rd line: the source of KBC F/W -- American Megatrends Incorporated 4th line: the tracking code 821 : packages made in '98, week assembly house ID; A means ASE, S means SPIL.... etc. ...
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... Detail F Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 -144 - W83977EF Dimension in mm Dimension in inch Symbol Min Nom Min Nom Max A 0.25 0.35 0.45 0.010 0.014 1 A 2.57 2.72 2.87 ...