tps54388-q1

Manufacturer Part Numbertps54388-q1
Description
ManufacturerTexas Instruments Incorporated
tps54388-q1 datasheet
 


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2.95-V to 6-V Input, 3-A Output, 2-MHz, Synchronous Step-Down
Switcher With Integrated FETs ( SWIFT™)
FEATURES
1
Qualified for Automotive Applications
2
Two 12-mΩ (typical) MOSFETs for High
Efficiency at 3-A Loads
200 kHz to 2 MHz Switching Frequency
0.8 V ± 1% Voltage Reference Over
Temperature (–40°C to 150°C)
Synchronizes to External Clock
Adjustable Slow Start/Sequencing
UV and OV Power Good Output
–40°C to 150°C Operating Junction
Temperature Range
Thermally Enhanced 3mm × 3mm 16-pin QFN
Pin Compatible to TPS54418
APPLICATIONS
Low-Voltage, High-Density Power Systems
Point of Load Regulation for High Performance
DSPs, FPGAs, ASICs and Microprocessors
Broadband, Networking and Optical
Communications Infrastructure
SIMPLIFIED SCHEMATIC
vertical spacer
vertical spacer
VIN
C
BOOT
VIN
BOOT
C I
R 4
TPS54388-Q1
EN
PH
R 5
PWRGD
VSENSE
SS/TR
RT /CLK
GND
COMP
AGND
C ss
POWERPAD
R T
R 3
C 1
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SWIFT, SwitcherPro, PowerPAD are trademarks of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Check for Samples:
TPS54388-Q1
DESCRIPTION
The TPS54388-Q1 device is a full featured 6 V, 3 A,
synchronous step down current mode converter with
two integrated MOSFETs.
The
TPS54388-Q1
integrating the MOSFETs, implementing current
mode control to reduce external component count,
reducing inductor size by enabling up to 2 MHz
switching frequency, and minimizing the IC footprint
with a small 3 mm x 3 mm thermally enhanced QFN
package.
The TPS54388-Q1 provides accurate regulation for a
variety of loads with an accurate ±1% Voltage
Reference (VREF) over temperature.
Efficiency is maximized through the integrated 12 mΩ
MOSFETs and 515 μA typical supply current. Using
the enable pin, shutdown supply current is reduced to
5.5 µA by entering a shutdown mode.
Under voltage lockout is internally set at 2.45 V, but
can be increased by programming the threshold with
a resistor network on the enable pin. The output
voltage startup ramp is controlled by the slow start
pin. An open drain power good signal indicates the
output is within 93% to 107% of its nominal voltage.
Frequency fold back and thermal shutdown protects
the device during an over-current condition.
The TPS54388-Q1 is supported in the SwitcherPro™
Software Tool at www.ti.com/switcherpro.
For more SWIFT
website at www.ti.com/swift.
L O
VOUT
C O
100
R 1
95
90
R 2
85
80
75
70
65
60
55
50
0
TPS54388-Q1
SLVSAF1A – OCTOBER 2010 – REVISED JUNE 2011
enables
small
designs
TM
documentation, see the TI
3 Vin
5 Vin
f = 500kHz
s
Vout = 1.8V
1
2
3
4
5
I - Output Current - A
O
Copyright © 2010–2011, Texas Instruments Incorporated
by
6

tps54388-q1 Summary of contents

  • Page 1

    ... Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Check for Samples: TPS54388-Q1 DESCRIPTION The TPS54388-Q1 device is a full featured synchronous step down current mode converter with two integrated MOSFETs. The TPS54388-Q1 integrating the MOSFETs, implementing current ...

  • Page 2

    ... TPS54388-Q1 SLVSAF1A – OCTOBER 2010 – REVISED JUNE 2011 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. T PACKAGE J –40°C to 150°C QFN – RTE ...

  • Page 3

    ... Copyright © 2010–2011, Texas Instruments Incorporated SLVSAF1A – OCTOBER 2010 – REVISED JUNE 2011 (1) (2) (3) (4) TPS54388-Q1 TPS54388-Q1 (RTE) UNITS (QFN-16) PINS 56.4 37 0.9 22.2 ° ...

  • Page 4

    ... TPS54388-Q1 SLVSAF1A – OCTOBER 2010 – REVISED JUNE 2011 ELECTRICAL CHARACTERISTICS T = –40°C to 150°C, VIN = 2. (unless otherwise noted) J DESCRIPTION SUPPLY VOLTAGE (VIN PIN) Operating input voltage Internal under voltage lockout threshold Shutdown supply current Quiescent Current - I q ENABLE AND UVLO (EN PIN) ...

  • Page 5

    ... VSENSE falling (Fault) VSENSE rising (Good) VSENSE rising (Fault) VSENSE falling (Good) VSENSE falling VSENSE = VREF 5.5 V (PWRGD (PWRGD) V < 0 100 μA (PWRGD) TPS54388-Q1 SLVSAF1A – OCTOBER 2010 – REVISED JUNE 2011 MIN TYP MAX UNIT 75 ns 120 60 ns 2.25 V/ Ω ...

  • Page 6

    ... TPS54388-Q1 SLVSAF1A – OCTOBER 2010 – REVISED JUNE 2011 PIN CONFIGURATION VIN VIN GND GND PIN NAME NO. AGND 5 Analog Ground should be electrically connected to GND close to the device. BOOT 13 A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the BOOT UVLO, the output is forced to switch off until the capacitor is refreshed ...

  • Page 7

    ... Threshold Minimum COMP Clamp PWM Comparator Logic and PWM Latch Slope S Compensation Frequency Shift Oscillator with PLL TPS54388-Q1 Block Diagram RT/CLK POWERPAD TPS54388-Q1 SLVSAF1A – OCTOBER 2010 – REVISED JUNE 2011 VIN UVLO Shutdown Logic Boot Charge Boot Current UVLO Sense ...

  • Page 8

    ... TPS54388-Q1 SLVSAF1A – OCTOBER 2010 – REVISED JUNE 2011 TYPICAL CHARACTERISTICS CURVES HIGH SIDE AND LOW SIDE R DS(ON) 0.025 0.023 High Side Rdson Vin = 3.3 V 0.021 Low Side Rdson Vin = 3.3 V 0.019 0.017 0.015 0.013 High Side Rdson Vin = 5 V 0.011 Low Side Rdson Vin = 5 V ...

  • Page 9

    ... CHARGE CURRENT vs TEMPERATURE -1.4 Vin = 5 V -1.6 -1.8 -2 -2.2 -2.4 -2.6 -2.8 -3 -50 -30 -10 100 125 150 TPS54388-Q1 SLVSAF1A – OCTOBER 2010 – REVISED JUNE 2011 JUNCTION TEMPERATURE 100 125 150 T - Junction Temperature - °C J Figure 100 125 150 T - Junction Temperature - °C J Figure 10 ...

  • Page 10

    ... TPS54388-Q1 SLVSAF1A – OCTOBER 2010 – REVISED JUNE 2011 TYPICAL CHARACTERISTICS CURVES (continued) INPUT VOLTAGE vs TEMPERATURE 2.8 2.7 2.6 UVLO Stop Switching 2.5 2.4 2.3 UVLO Start Switching 2.2 2.1 2 -50 - Junction Temperature - °C J Figure 13. SHUTDOWN SUPPLY CURRENT vs INPUT VOLTAGE 25° ...

  • Page 11

    ... RT/CLK pin. The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power switch turn falling edge of an external system clock. The TPS54388-Q1 has a typical default start up voltage of 2.45 V. The EN pin has an internal pull-up current source that can be used to adjust the input voltage under voltage lockout (UVLO) with two external resistors. In addition, the pull up current provides a default condition when the EN pin is floating for the device to operate. The total operating current for the TPS54388-Q1 is typically 515 μ ...

  • Page 12

    ... A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating higher is recommended because of the stable characteristics over temperature and voltage. To improve drop out, the TPS54388-Q1 is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is greater than 2.2 V. The high side MOSFET is turned off using an UVLO circuit, allowing for the low side MOSFET to conduct when the voltage from BOOT to PH drops below 2 ...

  • Page 13

    ... ENABLE AND ADJUSTING UNDER-VOLTAGE LOCKOUT The TPS54388-Q1 is disabled when the VIN pin voltage falls below 2 application requires a higher under-voltage lockout (UVLO), use the EN pin as shown in two external resistors recommended to use the EN resistors to set the UVLO falling threshold (V 2 ...

  • Page 14

    ... SLVSAF1A – OCTOBER 2010 – REVISED JUNE 2011 SLOW START/TRACKING PIN The TPS54388-Q1 regulates to the lower of the SS/TR pin and the internal reference voltage. A capacitor on the SS/TR pin to ground implements a slow start time. The TPS54388-Q1 has an internal pull-up current source of 2 μA which charges the external slow start capacitor. ...

  • Page 15

    ... Vout2 Equation 7 is the voltage difference between Vout1 and Equation 7 for ΔV. Equation 7 Equation 8 to ensure the device can recover from a fault. As TPS54388-Q1 SLVSAF1A – OCTOBER 2010 – REVISED JUNE 2011 Vout2 will result in a positive number for (5) (6) (7) (8) ...

  • Page 16

    ... Sequence CONSTANT SWITCHING FREQUENCY and TIMING RESISTOR (RT/CLK Pin) The switching frequency of the TPS54388-Q1 is adjustable over a wide range from 200 kHz to 2000 kHz by placing a maximum of 700 kΩ and minimum of 85 kΩ, respectively, on the RT/CLK pin. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. The RT/CLK is typically 0 ...

  • Page 17

    ... REVERSE OVERCURRENT PROTECTION The TPS54388-Q1 implements low side current protection by detecting the voltage across the low side MOSFET. When the converter sinks current through its low side FET, the control circuit turns off the low side MOSFET if the reverse current is typically more than 4 implementing this additional protection scheme, the converter is able to protect itself from excessive current during power cycling and start-up into pre-biased outputs ...

  • Page 18

    ... ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in transconductance. The gm for the TPS54388- A/V. The low frequency gain of the power stage frequency response is the product of the transconductance and the load resistance as shown in current increases and decreases, the low frequency gain decreases and increases, respectively ...

  • Page 19

    ... ESR SMALL SIGNAL MODEL FOR FREQUENCY COMPENSATION The TPS54388-Q1 uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used frequency compensation circuits. The compensation circuits are shown in circuits are most likely implemented in high bandwidth power supply designs using low ESR output capacitors. In Type 2A, one additional high frequency pole is added to attenuate high frequency noise ...

  • Page 20

    ... TPS54388-Q1 SLVSAF1A – OCTOBER 2010 – REVISED JUNE 2011 The design guidelines for TPS54388-Q1 loop compensation are as follows: 1. The modulator pole, fpmod, and the esr zero, fz1 must be calculated using Derating the output capacitor (C capacitor rating. Use the capacitor manufacturer information to derate the capacitor value. Use ...

  • Page 21

    ... Equation chosen in the design. Figure 34. High Frequency, 1.8 V Output Power Supply Design with Adjusted UVLO OUTPUT INDUCTOR SELECTION The inductor selected works for the entire TPS54388-Q1 input voltage range. To calculate the value of the output inductor, use Equation 22 coefficient that represents the amount of inductor ripple current relative to the IND maximum output current ...

  • Page 22

    ... TPS54388-Q1 SLVSAF1A – OCTOBER 2010 – REVISED JUNE 2011 For this design example, use K IND nearest standard value was chosen: 1.5 μH. For the output filter inductor important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from ...

  • Page 23

    ... L1 INPUT CAPACITOR The TPS54388-Q1 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7 μF of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54388-Q1 ...

  • Page 24

    ... Vref - Due to the internal design of the TPS54388-Q1, there is a minimum output voltage limit for any given input voltage. The output voltage can never be lower than the internal voltage reference of 0.827 V. Above 0.827 V, the output voltage may be limited by the minimum controllable on time. The minimum output voltage in this case ...

  • Page 25

    ... For most conditions, the regulator has a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54388-Q1. Since the slope compensation is ignored, the actual cross over frequency is usually lower than the cross over frequency used in the calculations. Use ...

  • Page 26

    ... TPS54388-Q1 SLVSAF1A – OCTOBER 2010 – REVISED JUNE 2011 APPLICATION CURVES EFFICIENCY vs LOAD CURRENT 100 3.3 Vin,1.8 Vout Vin, 1.8 Vout 0.5 1 1.5 Output Current - A Figure 35. EFFICIENCY vs LOAD CURRENT 1 MHz, 3.3 VIN 100 1. 0 ...

  • Page 27

    ... Time = 500 nsec / div Figure 44. CLOSED LOOP RESPONSE, VIN (5 V –10 –20 –30 –40 Gain –50 Phase –60 10 100 1000 10k 100k Frequency - Hz Figure 46. TPS54388-Q1 180 150 120 –30 –60 –90 –120 –150 –180 1M 27 ...

  • Page 28

    ... TPS54388-Q1 SLVSAF1A – OCTOBER 2010 – REVISED JUNE 2011 LOAD REGULATION vs LOAD CURRENT 0.4 0.3 0.2 Vin = 5 V 0.1 0 Vin = 3.3 V -0.1 -0.2 -0.3 -0.4 0 0.5 1 1.5 Output Current - A Figure 47. POWER DISSIPATION ESTIMATE The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM) operation. The power dissipation of the IC (Ptot) includes conduction loss (Pcon), dead time loss (Pd), switching loss (Psw), gate drive loss (Pgd) and supply current loss (Pq) ...

  • Page 29

    ... PCB layouts, however this layout has been shown to produce good results and is meant as a guideline. Copyright © 2010–2011, Texas Instruments Incorporated SLVSAF1A – OCTOBER 2010 – REVISED JUNE 2011 Figure 49 for a PCB layout example. The GND pins and TPS54388-Q1 29 ...

  • Page 30

    ... TPS54388-Q1 SLVSAF1A – OCTOBER 2010 – REVISED JUNE 2011 UVLO SET RESISTORS VIN VIN INPUT VIN BYPASS CAPACITOR VIN GND GND FEEDBACK RESISTORS TOPSIDE GROUND AREA 30 VIA to Ground Plane BOOT CAPACITOR PH PH EXPOSED POWERPAD PH AREA PH SS SLOW START CAPACITOR ANALOG GROUND ...

  • Page 31

    ... PACKAGING INFORMATION Orderable Device (1) Package Type Package Status TPS54388QRTERQ1 ACTIVE WQFN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. ...

  • Page 32

    ... TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing TPS54388QRTERQ1 WQFN RTE PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 16 3000 330.0 12.4 3.3 Pack Materials-Page 1 16-Jun-2011 Pin1 (mm) (mm) (mm) (mm) Quadrant 3.3 1.1 8.0 12.0 Q2 ...

  • Page 33

    ... Device Package Type TPS54388QRTERQ1 WQFN PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) RTE 16 3000 Pack Materials-Page 2 16-Jun-2011 Width (mm) Height (mm) 346.0 346.0 29.0 ...

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    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...