hcs373ms Intersil Corporation, hcs373ms Datasheet
hcs373ms
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hcs373ms Summary of contents
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... Output Enable. The HCS373MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS373MS is supplied lead Ceramic flatpack (K suffi SBDIP Package (D suffix). Ordering Information PART NUMBER ...
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... COMMON CONTROLS LE (11 High Level Low Level X = Immaterial Low voltage level prior to the high-to-low latch enable transition h = High voltage level prior to the high-to-low latch enable transition HCS373MS LATCH TRUTH TABLE ...
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... Functional Test VIH = 0.70(VCC), VIL = 0.30(VCC), (Note 2) NOTES: 1. All voltages reference to device GND. 2. For functional tests VO 4.0V is recognized as a logic “1”, and VO Specifications HCS373MS Reliability Information Thermal Resistance SBDIP Package 10mA Ceramic Flatpack Package . . . . . . . . . . . 25mA Maximum Package Power Dissipation at +125 SBDIP Package ...
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... The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. Specifications HCS373MS GROUP (NOTES 1, 2) ...
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... AC measurements assume RL = 500 , CL = 50pF, Input 3ns, VIL = GND, VIH = VCC. 3. For functional tests VO 4.0V is recognized as a logic “1”, and VO TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25 PARAMETER ICC IOL/IOH IOZL/IOZH Specifications HCS373MS (NOTES 1, 2) CONDITIONS TEMPERATURE 0.5V is recognized as a logic “0”. GROUP B SUBGROUP DELTA LIMIT ...
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... Each pin except VCC and GND will have a resistor of 680 OPEN 12, 15, 16, 19 NOTE: Each pin except VCC and GND will have a resistor of 47K E, Subgroup 2, sample size is 4 dice/wafer 0 failures. Specifications HCS373MS TABLE 6. APPLICABLE SUBGROUPS METHOD GROUP A SUBGROUPS 100%/5004 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com HCS373MS 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition hrs ...
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... DATA VS VS TPLH TPLH Qn VS FIGURE 1. LATCH ENABLE PROPAGATION DELAYS TTLH VOH 80% 20% OUTPUT VOL FIGURE 3. OUTPUT TRANSITION TIMES AC Load Circuit HCS373MS VS INPUT LEVEL DATA TPHL TH(L) TPHL VS LE FIGURE 2. LATCH ENABLE PREREQUISITE TIMES (DATA SET-UP AND HOLD) PARAMETER VCC VIH TTHL ...
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... Three-State High Timing Diagram VIH OE INPUT VS VIL TPHZ VOH VW OUTPUT VOZ THREE-STATE HIGH VOLTAGE LEVELS PARAMETER HCS VCC 4.50 VIH 4.50 VS 2.25 VT 2.25 VW 3.60 GND 0 VIL 0 HCS373MS Three-State Load Circuit TPLZ CL = 50pF 500 UNITS Three-State Load Circuit TPZH VT UNITS 354 VCC RL ...
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... D1 (4) Q1 (5) Q2 (6) D2 (7) (8) D3 NOTE: The die diagram is a generic plot from a similar HCS device intended to indicate approximate die size and bond pad location. The mask series for the HCS373 is TA14303A. HCS373MS HCS373MS Q0 OE VCC (2) (1) (20) (19) (9) (10) (11) ...