attiny13-20ss ATMEL Corporation, attiny13-20ss Datasheet - Page 21

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attiny13-20ss

Manufacturer Part Number
attiny13-20ss
Description
8-bit Microcontroller With 1k Bytes In-system Programmable Flash - Atmel Corporation
Manufacturer
ATMEL Corporation
Datasheet

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System Clock and
Clock Options
Clock Systems and their
Distribution
CPU Clock – clk
I/O Clock – clk
Flash Clock – clk
ADC Clock – clk
2535G–AVR–01/07
I/O
CPU
ADC
FLASH
Figure 11 presents the principal clock systems in the AVR and their distribution. All of
the clocks need not be active at a given time. In order to reduce power consumption, the
clocks to modules not being used can be halted by using different sleep modes, as
described in “Power Management and Sleep Modes” on page 27. The clock systems
are detailed below.
Figure 11. Clock Distribution
The CPU clock is routed to parts of the system concerned with operation of the AVR
core. Examples of such modules are the General Purpose Register File, the Status Reg-
ister and the Data memory holding the Stack Pointer. Halting the CPU clock inhibits the
core from performing general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O
clock is also used by the External Interrupt module, but note that some external inter-
rupts are detected by asynchronous logic, allowing such interrupts to be detected even if
the I/O clock is halted.
The Flash clock controls operation of the Flash interface. The Flash clock is usually
active simultaneously with the CPU clock.
The ADC is provided with a dedicated clock domain. This allows halting the CPU and
I/O clocks in order to reduce noise generated by digital circuitry. This gives more accu-
rate ADC conversion results.
ADC
clk
ADC
General I/O
Modules
External Clock
clk
I/O
Control Unit
AVR Clock
Multiplexer
Clock
Source clock
Reset Logic
CPU Core
clk
clk
CPU
FLASH
Watchdog Timer
Watchdog clock
RAM
Watchdog
Oscillator
Flash and
EEPROM
Calibrated RC
Oscillator
21

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