attiny13-20ss ATMEL Corporation, attiny13-20ss Datasheet - Page 25

• Manufacturer Part Number: attiny13-20ss
• Description: 8-bit Microcontroller With 1k Bytes In-system Programmable Flash - Atmel Corporation
• Manufacturer: ATMEL Corporation

128 kHz Internal
Oscillator
System Clock Prescaler
Clock Prescale Register –
CLKPR
2535G–AVR–01/07
The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz.
The frequency is nominal at 3V and 25#C. This clock may be select as the system clock
by programming the CKSEL Fuses to “11”.
When this clock source is selected, start-up times are determined by the SUT Fuses as
shown in Table 8.
Table 8. Start-up Times for the 128 kHz Internal Oscillator
The ATtiny13 system clock can be divided by setting the Clock Prescale Register –
CLKPR. This feature can be used to decrease power consumption when the require-
ment for processing power is low. This can be used with all clock source options, and it
will affect the clock frequency of the CPU and all synchronous peripherals. clk
clk
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The
CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to
zero. CLKPCE is cleared by hardware four cycles after it is written or when the CLKPS
bits are written. Rewriting the CLKPCE bit within this time-out period does neither
extend the time-out period, nor clear the CLKPCE bit.
• Bits 6..4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal
system clock. These bits can be written run-time to vary the clock frequency to suit the
application requirements. As the divider divides the master clock input to the MCU, the
speed of all synchronous peripherals is reduced when a division factor is used. The divi-
sion factors are given in Table 9.
To avoid unintentional changes of clock frequency, a special write procedure must be
followed to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits
2. Within four cycles, write the desired value to CLKPS while writing a zero to
Interrupts must be disabled when changing prescaler setting to make sure the write pro-
cedure is not interrupted.
Bit
Read/Write
Initial Value
SUT1..0
CPU
00
01
10
11
in CLKPR to zero.
CLKPCE.
, and clk
Start-up Time from Power-
CLKPCE
down and Power-save
FLASH
R/W
7
0
are divided by a factor as shown in Table 9.
6 CK
6 CK
6 CK
R
6
–
0
R
5
–
0
R
4
0
–
Additional Delay from
Reserved
14CK + 64 ms
14CK + 4 ms
CLKPS3
R/W
Reset
14CK
3
CLKPS2
See Bit Description
R/W
2
CLKPS1
R/W
Recommended Usage
BOD enabled
Fast rising power
Slowly rising power
1
CLKPS0
R/W
0
I/O
, clk
CLKPR
ADC
25
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