attiny13-20ss ATMEL Corporation, attiny13-20ss Datasheet - Page 66

• Manufacturer Part Number: attiny13-20ss
• Description: 8-bit Microcontroller With 1k Bytes In-system Programmable Flash - Atmel Corporation
• Manufacturer: ATMEL Corporation

Phase Correct PWM Mode
66
ATtiny13
The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase
correct PWM waveform generation option. The phase correct PWM mode is based on a
dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then
from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when
WGM2:0 = 5. In non-inverting Compare Output mode, the Output Compare (OC0x) is
cleared on the Compare Match between TCNT0 and OCR0x while upcounting, and set
on the Compare Match while down-counting. In inverting Output Compare mode, the
operation is inverted. The dual-slope operation has lower maximum operation frequency
than single slope operation. However, due to the symmetric feature of the dual-slope
PWM modes, these modes are preferred for motor control applications.
In phase correct PWM mode the counter is incremented until the counter value matches
TOP. When the counter reaches TOP, it changes the count direction. The TCNT0 value
will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct
PWM mode is shown on Figure 32. The TCNT0 value is in the timing diagram shown as
a histogram for illustrating the dual-slope operation. The diagram includes non-inverted
and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes repre-
sent Compare Matches between OCR0x and TCNT0.
Figure 32. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOT-
TOM. The Interrupt Flag can be used to generate an interrupt each time the counter
reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on
the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An
inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the
COM0A0 bits to one allows the OC0A pin to toggle on Compare Matches if the WGM02
bit is set. This option is not available for the OC0B pin (See Table 28 on page 70). The
actual OC0x value will only be visible on the port pin if the data direction for the port pin
is set as output. The PWM waveform is generated by clearing (or setting) the OC0x
Register at the Compare Match between OCR0x and TCNT0 when the counter incre-
ments, and setting (or clearing) the OC0x Register at Compare Match between OCR0x
TCNTn
OCn
OCn
Period
1
2
3
OCnx Interrupt Flag Set
OCRnx Update
TOVn Interrupt Flag Set
(COMnx1:0 = 2)
(COMnx1:0 = 3)
2535G–AVR–01/07