atmega103 ATMEL Corporation, atmega103 Datasheet - Page 35

• Manufacturer Part Number: atmega103
• Description: Atmega103 8-bit With 128k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

Timer/Counter Interrupt Flag
Register – TIFR
0945I–AVR–02/07
• Bit 7 – OCF2: Output Compare Flag 2:
The OCF2 bit is set (one) when compare match occurs between Timer/Counter2 and
the data in OCR2 – Output Compare Register 2. OCF2 is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by
writing a logical “1” to the flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2
Compare Interrupt Enable) and the OCF2 are set (one), the Timer/Counter2 Output
Compare interrupt is executed.
• Bit 6 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV2 is cleared by writing a logical “1” to the flag. When the I-bit in SREG, and TOIE2
(Tim er/Co un ter1 Ove rflow Inte rrup t En able) an d TO V2 a re set (o ne) , th e
Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when
Timer/Counter2 advances from $00.
• Bit 5 – ICF1: Input Capture Flag 1
The ICF1 bit is set (one) to flag an Input Capture event, indicating that the
Timer/Counter1 value has been transferred to the Input Capture Register (ICR1). ICF1
is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ICF1 is cleared by writing a logical “1” to the flag. When the SREG I-bit,
TICIE1 (Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the
Timer/Counter1 Capture interrupt is executed.
• Bit 4 – OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1
and the data in OCR1A – Output Compare Register 1A. OCF1A is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF1A is
cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1A
(Timer/Counter1 Compare Interrupt Enable) and the OCF1A are set (one), the
Timer/Counter1 Compare A Match interrupt is executed.
• Bit 3 – OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1
and the data in OCR1B – Output Compare Register 1B. OCF1B is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF1B is
cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1B
(Timer/Counter1 Compare Match Interrupt Enable) and the OCF1B are set (one), the
Timer/Counter1 Compare B Match interrupt is executed.
• Bit 2 – TOV1: Timer/Counter1 Overflow Flag
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV1 is cleared by writing a logical “1” to the flag. When the I-bit in SREG and TOIE1
Bit
$36 ($56)
Read/Write
Initial Value
OCF2
R/W
7
0
TOV2
R/W
6
0
ICF1
R/W
5
0
OCF1A
R/W
4
0
OCF1B
R/W
3
0
TOV1
R/W
ATmega103(L)
2
0
OCF0
R/W
1
0
TOV0
R/W
0
0
TIFR
35