atmega103 ATMEL Corporation, atmega103 Datasheet - Page 44

• Manufacturer Part Number: atmega103
• Description: Atmega103 8-bit With 128k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

Asynchronous Status
Register – ASSR
44
ATmega103(L)
Figure 32. Effects on Unsynchronized OCR Latching
During the time between the write and the latch operation, a read from OCR0 or OCR2
will read the contents of the temporary location. This means that the most recently writ-
ten value always will read out of OCR0/2.
When the OCR Register (not the temporary register) is updated to $00 or $FF, the PWM
output changes to low or high immediately according to the settings of COM21/COM20
or COM11/COM10. This is shown in Table 14.
Table 14. PWM Outputs OCRn = $00 or $FF
Note:
In PWM mode, the Timer Overflow Flag, TOV0 or TOV2, is set when the counter
advances from $00. Timer Overflow Interrupts 0 and 2 operate exactly as in normal
Timer/Counter mode, i.e., it is executed when TOV0 or TOV2 is set, provided that Timer
Overflow interrupt and Global Interrupts are enabled. This also applies to the Timer Out-
put Compare Flags and interrupts.
The frequency of the PWM will be Timer Clock Frequency divided by 510.
• Bits 7..4 – Res: Reserved Bits
These bits are reserved bits in the ATmega103(L) and always read as zero.
Bit
$30 ($50)
Read/Write
Initial Value
COMn1
n = 0 or 2
1
1
1
1
Compare Value changes
R
7
–
0
Compare Value changes
Unsynchronized OCR Latch
R
6
–
0
Synchronized OCR Latch
COMn0
0
0
1
1
R
5
–
0
R
4
0
–
OCRn
R/W
AS0
$FF
$FF
$00
$00
3
0
TCN0UB
R
2
0
Glitch
OCR0UB
R
1
0
Output PWMn
Counter Value
Compare Value
PWM Output
Counter Value
Compare Value
PWM Output
TCR0UB
H
H
L
L
R
0
0
0945I–AVR–02/07
ASSR