atmega103 ATMEL Corporation, atmega103 Datasheet - Page 63

• Manufacturer Part Number: atmega103
• Description: Atmega103 8-bit With 128k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

SPI Status Register – SPSR
0945I–AVR–02/07
• Bit 5 – DORD: Data Order
When the DORD bit is set (one), the LSB of the data word is transmitted first.
When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared
(zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be
cleared and SPIF in SPSR will become set. The user will then have to set MSTR to re-
enable SPI Master mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is
low when idle. Refer to Figure 39 and Figure 40 for additional information.
• Bit 2 – CPHA: Clock Phase
Refer to Figure 39 or Figure 40 for the functionality of this bit.
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and
SPR0 have no effect on the Slave. The relationship between SCK and the CPU Clock
frequency (f
Table 23. Relationship between SCK and the Oscillator Frequency
Note:
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is gener-
ated if SPIE in SPCR is set (one) and Global Interrupts are enabled. SPIF is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively, the
SPIF bit is cleared by first reading the SPI Status Register with SPIF set (one), then
accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.
The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Reg-
ister with WCOL set (one), and then accessing the SPI Data Register.
Bit
$0E
Read/Write
Initial Value
SPR1
Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL
divider is enabled.
0
0
1
1
cl
) is shown in Table 23.
SPIF
R
7
0
WCOL
R
6
0
SPR0
0
1
0
1
R
5
–
0
R
4
–
0
3
–
R
0
R
SCK Frequency
2
–
0
ATmega103(L)
f
f
f
cl
f
cl
cl
cl
/
/
/
128
/
16
64
R
1
–
0
4
R
0
–
0
SPSR
63