Manufacturer Part Numberat90s2323
Description8-bit Microcontroller With 2k Bytes Of In-system Programmable Flash At90s2323 At90ls2323 At90s2343 At90ls2343
ManufacturerATMEL Corporation
at90s2323 datasheet
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Utilizes the AVR
RISC Architecture
AVR – High-performance and Low-power RISC Architecture
– 118 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General-purpose Working Registers
– Up to 10 MIPS Throughput at 10 MHz
Data and Nonvolatile Program Memory
– 2K Bytes of In-System Programmable Flash
Endurance: 1,000 Write/Erase Cycles
– 128 Bytes Internal RAM
– 128 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– Programmable Watchdog Timer with On-chip Oscillator
– SPI Serial Interface for In-System Programming
Special Microcontroller Features
– Low-power Idle and Power-down Modes
– External and Internal Interrupt Sources
– Power-on Reset Circuit
– Selectable On-chip RC Oscillator
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
Power Consumption at 4 MHz, 3V, 25°C
– Active: 2.4 mA
– Idle Mode: 0.5 mA
– Power-down Mode: <1 µA
I/O and Packages
– Three Programmable I/O Lines for AT90S/LS2323
– Five Programmable I/O Lines for AT90S/LS2343
– 8-pin PDIP and SOIC
Operating Voltages
– 4.0 - 6.0V for AT90S2323/AT90S2343
– 2.7 - 6.0V for AT90LS2323/AT90LS2343
Speed Grades
– 0 - 10 MHz for AT90S2323/AT90S2343-10
– 0 - 4 MHz for AT90LS2323/AT90LS2343-4
– 0 - 1 MHz for AT90LS2343-1
Pin Configuration
PB2 (SCK/T0)
PB2 (SCK/T0)
with 2K Bytes of
Rev. 1004D–09/01

at90s2323 Summary of contents

  • Page 1

    ... Five Programmable I/O Lines for AT90S/LS2343 – 8-pin PDIP and SOIC • Operating Voltages – 4.0 - 6.0V for AT90S2323/AT90S2343 – 2.7 - 6.0V for AT90LS2323/AT90LS2343 • Speed Grades – MHz for AT90S2323/AT90S2343-10 – MHz for AT90LS2323/AT90LS2343-4 – MHz for AT90LS2343-1 Pin Configuration RESET 1 8 VCC ...

  • Page 2

    ... The AT90S/LS2323 and AT90S/LS2343 are low-power, CMOS, 8-bit microcontrollers based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S2323/2343 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general-purpose working regis- ters ...

  • Page 3

    ... PROGRAMMING SPI LOGIC DATA REGISTER The AT90S2323/2343 provides the following features: 2K bytes of In-System Program- mabl e Flash, 128 bytes EEPROM, 128 bytes SRAM T90S/LS2323)/5 (AT90S/LS2343) general-purpose I/O lines, 32 general-purpose working registers bit timer/counter, internal and external interrupts, programmable Watchdog Timer with internal oscillator, an SPI serial port for Flash Memory downloading and two software- selectable power-saving modes ...

  • Page 4

    ... Atmel AT90S2323/2343 is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications. The AT90S2323/2343 AVR is supported with a full suite of program and system devel- opment tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators and evaluation kits. ...

  • Page 5

    Pin Descriptions AT90S/LS2343 VCC GND Port B (PB4..PB0) RESET CLOCK Clock Options Crystal Oscillator External Clock 1004D–09/01 Supply voltage pin. Ground pin. Port 5-bit bi-directional I/O port with internal pull-up resistors. The Port B output buffers can ...

  • Page 6

    AT90S/LS2323/2343 6 Figure 4. External Clock Drive Configuration AT90S/LS2343 EXTERNAL PB3 OSCILATOR SIGNAL GND AT90S/LS2323 XTAL2 NC EXTERNAL OSCILATOR XTAL1 SIGNAL GND 1004D–09/01 ...

  • Page 7

    ... The ALU supports arithmetic and logic functions between registers or between a con- stant and a register. Single register operations are also executed in the ALU. Figure 5 shows the AT90S2323/2343 AVR RISC microcontroller architecture. In addition to the register operation, the conventional memory addressing modes can be used on the register file as well. This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations ...

  • Page 8

    AT90S/LS2323/2343 8 The AVR has Harvard architecture – with separate memories and buses for program and data. The program memory is accessed with a two-stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program ...

  • Page 9

    General-purpose Register File 1004D–09/01 Figure 7 shows the structure of the 32 general-purpose registers in the CPU. Figure 7. AVR CPU General-purpose Working Registers 7 General Purpose Working Registers All the register operating instructions in the instruction set have direct ...

  • Page 10

    ... Memory instruction description on page 60). See page 12 for the different addressing modes. The AT90S2323/2343 contains 128 bytes of EEPROM data memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 32, specifying the EEPROM address register, the EEPROM data register and the EEPROM control register ...

  • Page 11

    ... When using register indirect addressing modes with automatic pre-decrement and post- increment, the address registers X, Y, and Z are used and decremented and incremented. The 32 general-purpose working registers, 64 I/O registers and the 128 bytes of data SRAM in the AT90S2323/2343 are all directly accessible through all these addressing modes. AT90S/LS2323/2343 Data Address Space ...

  • Page 12

    ... Rd and Rr AT90S/LS2323/2343 12 The AT90S2323/2343 AVR RISC microcontroller supports powerful and efficient addressing modes for access to the program memory (Flash) and data memory. This section describes the different addressing modes supported by the AVR architecture. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits ...

  • Page 13

    I/O Direct Data Direct Data Indirect with Displacement 1004D–09/01 Figure 12. I/O Direct Addressing Operand address is contained in six bits of the instruction word the destination or source register address. Figure 13. Direct Data Addressing A 16-bit ...

  • Page 14

    Data Indirect Data Indirect with Pre- decrement Data Indirect with Post- increment AT90S/LS2323/2343 14 Figure 15. Data Indirect Addressing Operand address is the contents of the X-, Y-, or the Z-register. Figure 16. Data Indirect Addressing with Pre-decrement The X-, ...

  • Page 15

    Constant Addressing Using the LPM Instruction Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL 1004D–09/01 Figure 18. Code Memory Constant Addressing Constant byte address is specified by the Z-register contents. The 15 MSBs select word address ...

  • Page 16

    Memory Access and Instruction Execution Timing AT90S/LS2323/2343 16 This section describes the general access timing concepts for instruction execution and internal memory access. The AVR CPU is driven by the System Clock Ø, directly generated from the external clock signal ...

  • Page 17

    ... Note: Reserved and unused locations are not shown in the table. All AT90S2323/2343 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general- purpose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions ...

  • Page 18

    Status Register – SREG AT90S/LS2323/2343 18 and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as SRAM, $20 must be added to these addresses. All I/O register addresses throughout this document are shown with ...

  • Page 19

    ... Note that the Status Register is not automatically stored when entering an interrupt rou- tine and restored when returning from an interrupt routine. This must be handled by software bit r egister at I/O addres s $3D ( $5D) for ms the stack pointer of the AT90S2323/2343. Eight bits are used to address the 128 bytes of SRAM in locations $60 - $DF. Bit 7 ...

  • Page 20

    ... MAIN: ldi r16, low(RAMEND) out SPL, r16 <instr> xxx ... ... ... The AT90S2323/2343 provides three sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ). POT • External Reset. The MCU is reset when a low level is present on the RESET pin for more than 50 ns. • ...

  • Page 21

    ... The Power-on Reset will not work unless the supply voltage has been below V (falling). The AT90S2323/2343 is designed for use in systems where it can operate from the internal RC oscillator (AT90S/LS2343), on-chip oscillator (AT90S/LS2323 appli- cations where a clock signal is provided by an external clock source. After V ...

  • Page 22

    External Reset AT90S/LS2323/2343 22 Figure 25. MCU Start-up, RESET Tied POT VCC V RST RESET t TOUT TIME-OUT INTERNAL RESET Figure 26. MCU Start-up, RESET Controlled Externally V POT VCC RESET TIME-OUT INTERNAL RESET An external reset ...

  • Page 23

    ... Bits 7..2 – Res: Reserved Bits These bits are reserved bits in the AT90S2323/2343 and always read as zero. • Bit 1 – EXTRF: External Reset Flag After a Power-on Reset, this bit is undefined (X). It will be set by an External Reset. A Watchdog Reset will leave this bit unchanged. ...

  • Page 24

    ... Bit 7 – Res: Reserved Bit This bit is a reserved bit in the AT90S2323/2343 and always reads as zero. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled ...

  • Page 25

    ... Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $002) is executed if an overflow in Timer/Counter0 occurs, i.e., when the Overflow Flag (Timer/Counter0) is set (one) in the Timer/Counter Interrupt Flag Register (TIFR). • Bit 0 – Res: Reserved Bit This bit is a reserved bit in the AT90S2323/2343 and always reads as zero. Bit 7 6 $38 ($58) – ...

  • Page 26

    ... For details, refer to the section “Sleep Modes”. • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the AT90S2323/2343 and always read as zero. • Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set ...

  • Page 27

    Sleep Modes Idle Mode Power-down Mode 1004D–09/01 activate the interrupt are defined in Table 9. The value on the INT01 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock ...

  • Page 28

    ... Timer/Counter0 AT90S/LS2323/2343 28 The AT90S2323/2343 provides one general-purpose 8-bit Timer/Counter – Timer/Counter0. The Timer/Counter has prescaling selection from the 10-bit prescaling timer. The Timer/Counter can be used either as a timer with an internal clock time base counter with an external pin connection that triggers the counting. ...

  • Page 29

    ... Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90S2323/2343 and always read zero. • Bits – CS02, CS01, CS00: Clock Select0, Bits 2, 1 and 0 The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer/Counter0. ...

  • Page 30

    ... Reset) instruction resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog reset, the AT90S2323/2343 resets and executes from the reset vec- tor. For timing details on the Watchdog reset, refer to page 23. ...

  • Page 31

    ... Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the AT90S2323/2343 and will always read as zero. • Bit 4 – WDTOE: Watchdog Turn-off Enable This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. ...

  • Page 32

    ... Bit 7 – Res: Reserved Bit This bit is a reserved bit in the AT90S2323/2343 and will always read as zero. • Bit 6..0 – EEAR6..0: EEPROM Address The EEPROM Address Register (EEAR6..0) specifies the EEPROM address in the 128-byte EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 127 ...

  • Page 33

    ... Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90S2323/2343 and will always read as zero. • Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to “1” causes the EEPROM to be written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the selected address ...

  • Page 34

    Prevent EEPROM Corruption AT90S/LS2323/2343 34 During periods of low V , the EEPROM data can be corrupted because the supply volt- CC age is too low for the CPU and the EEPROM to operate properly. These issues are the same ...

  • Page 35

    I/O Port B Port B Data Register – PORTB Port B Data Direction Register – DDRB 1004D–09/01 All AVR ports have true read-modify-write functionality when used as general digital I/O ports. This means that the direction of one port pin ...

  • Page 36

    Port B Input Pins Address – PINB Port B as General Digital I/O Alternate Functions of Port B AT90S/LS2323/2343 36 Bit $16 ($36) – – – Read/Write Initial Value The Port ...

  • Page 37

    ... AT90S/LS2343 Signature Bytes 1004D–09/01 The AT90S2323/2343 MCU provides two Lock bits that can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 14. The Lock bits can only be erased with the Chip Erase operation. Table 14. Lock Bit Protection Modes ...

  • Page 38

    ... Atmel’s AT90S2323/2343 offers 2K bytes of In-System Programmable Flash program memory and 128 bytes of EEPROM data memory. The AT90S2323/2343 is shipped with the On-chip Flash program and EEPROM data memory arrays in the erased state (i.e., contents = $FF) and ready to be programmed. The device supports a high-voltage (12V) Serial Programming mode and a low-voltage Serial Programming mode ...

  • Page 39

    High-voltage Serial Programming Algorithm 1004D–09/01 To program and verify the AT90S/LS2323 and AT90S/LS234 in the high-voltage Serial Programming mode, the following sequence is recommended (see instruction formats in Table 16): 1. Power-up sequence: Apply 4.5 - 5.5V between V PB0 ...

  • Page 40

    Table 16. High-voltage Serial Programming Instruction Set Instruction Instr.1 PB0 0_1000_0000_00 Chip Erase PB1 0_0100_1100_00 PB2 x_xxxx_xxxx_xx PB0 0_0001_0000_00 Write Flash High and Low PB1 0_0100_1100_00 Address PB2 x_xxxx_xxxx_xx PB0 i_i _00 Write ...

  • Page 41

    Table 16. High-voltage Serial Programming Instruction Set (Continued) Instruction Instr.1 Read Fuse PB0 0_0000_0100_00 and Lock Bits PB1 0_0100_1100_00 (AT90S/ PB2 x_xxxx_xxxx_xx LS2323) Read Fuse PB0 0_0000_0100_00 and Lock Bits PB1 0_0100_1100_00 (AT90S/ PB2 x_xxxx_xxxx_xx LS2343) PB0 0_0000_1000_00 Read PB1 ...

  • Page 42

    High-voltage Serial Programming Characteristics Low-voltage Serial Downloading AT90S/LS2323/2343 42 Figure 34. High-voltage Serial Programming Timing SDI (PB0), SII (PB1) t SCI (XTAL1/PB3) SDO (PB2) Table 17. High-voltage Serial Programming Characteristics, T 5.0V ± 10% (unless otherwise noted) Symbol Parameter t ...

  • Page 43

    ... Low: > 2 MCU clock cycles High: > 2 MCU clock cycles When writing serial data to the AT90S2323/2343, data is clocked on the rising edge of SCK. When reading data from the AT90S2323/2343, data is clocked on the falling edge of SCK ...

  • Page 44

    ... EEPROM is reprogrammed without first chip-erasing the device. Table 18. Read Back Value during EEPROM Polling Part AT90S2323 AT90S2343 When a byte is being programmed into the Flash, reading the address location being programmed will give the value $FF. At the time the device is ready for a new byte, the programmed value will read correctly ...

  • Page 45

    ... Table 19. Low-voltage Serial Programming Instruction Set AT90S2323/2343 Instruction Byte 1 Programming 1010 1100 Enable 1010 1100 Chip Erase 0010 H000 Read Program Memory 0100 H000 Write Program Memory Read 1010 0000 EEPROM Memory Write 1100 0000 EEPROM Memory Read Lock and 0101 1000 ...

  • Page 46

    Low-voltage Serial Programming Characteristics AT90S/LS2323/2343 46 Figure 37. Low-voltage Serial Programming Timing MOSI t OVSH SCK MISO Table 20. Low-voltage Serial Programming Characteristics, T 2.7 - 6.0V (unless otherwise noted) Symbol Parameter 1/t Oscillator Frequency (V CLCL CC t Oscillator ...

  • Page 47

    ... I/O Pin Pull-up I/O Power Supply Current AT90S2343 I CC Power Supply Current AT90S2323 Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low. 2. “Min” means the lowest value where the pin is guaranteed to be read as high. 3. Minimum V for Power-down is 2V. CC 1004D– ...

  • Page 48

    External Clock Drive Waveforms AT90S/LS2323/2343 48 Figure 38. Waveforms VIH1 VIL1 External Clock Drive = -40 ° ° Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low ...

  • Page 49

    Typical Characteristics 1004D–09/01 The following charts show typical behavior. These figures are not tested during manu- facturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with ...

  • Page 50

    AT90S/LS2323/2343 50 Figure 40. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs 2.5 3 3.5 Figure 41. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. ...

  • Page 51

    Figure 42. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY 5 4.5 4 3.5 3 2.5 2 1 Figure 43. Idle Supply Current vs. V IDLE SUPPLY CURRENT ...

  • Page 52

    AT90S/LS2323/2343 52 Figure 44. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V DEVICE CLOCKED BY INTERNAL RC OSCILLATOR 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 2.5 3 3.5 Figure 45. Power-down Supply Current vs. V ...

  • Page 53

    Figure 46. Power-down Supply Current vs. V POWER DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 180 160 140 120 100 2.5 3 Figure 47. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY ...

  • Page 54

    AT90S/LS2323/2343 54 Note: Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 48. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 120 ˚ A 100 ...

  • Page 55

    Figure 50. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 1 Figure 51. I/O PIn Source Current vs. Output Voltage I/O PIN SOURCE ...

  • Page 56

    AT90S/LS2323/2343 56 Figure 52. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 Figure 53. I/O Pin Source Current vs. Output voltage I/O PIN SOURCE CURRENT vs. ...

  • Page 57

    Figure 54. I/O Pin Input Threshold Voltage vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs. V 2.5 2 1.5 1 0.5 0 2.7 Figure 55. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V 0.18 0.16 ...

  • Page 58

    ... AT90S2323/2343 Register Summary Address Name Bit 7 $3F ($5F) SREG I $3E ($5E) Reserved $3D ($5D) SPL SP7 $3C ($5C) Reserved $3B ($5B) GIMSK - $3A ($5A) GIFR - $39 ($59) TIMSK - $38 ($58) TIFR - $37 ($57) Reserved $36 ($56) Reserved $35 ($55) MCUCR - $34 ($54) MCUSR - $33 ($53) TCCR0 - $32 ($52) TCNT0 Timer/Counter0 (8 Bits) $31 ($51) Reserved $30 ($50) Reserved ...

  • Page 59

    Instruction Set Summary Mnemonic Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add Two Registers ADC Rd, Rr Add with Carry Two Registers ADIW Rdl, K Add Immediate to Word SUB Rd, Rr Subtract Two Registers SUBI Rd, K ...

  • Page 60

    Instruction Set Summary (Continued) Mnemonic Operands Description DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move between Registers LDI Rd, K Load Immediate LD Rd, X Load Indirect LD Rd, X+ Load Indirect and Post-inc. LD Rd, -X Load Indirect and Pre-dec. ...

  • Page 61

    ... Wide, Plastic Dual Inline Package (PDIP) 8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 1004D–09/01 Ordering Code 4 AT90LS2323-4PC AT90LS2323-4SC AT90LS2323-4PI AT90LS2323-4SI AT90S2323-10PC AT90S2323-10SC AT90S2323-10PI AT90S2323-10SI 1 AT90LS2343-1PC AT90LS2343-1SC AT90LS2343-1PI AT90LS2343-1SI 4 AT90LS2343-4PC AT90LS2343-4SC AT90LS2343-4PI AT90LS2343-4SI AT90S2343-10PC AT90S2343-10SC ...

  • Page 62

    Packaging Information 8P3 8P3, 8-lead, Plastic Dual Inline Package (PDIP), 0.300" Wide. Dimensions in Millimeters and (Inches)* JEDEC STANDARD MS-001 BA .300 (7.62) REF 5.33(0.210) MAX Seating Plane 3.81(0.150) 2.92(0.115) 0.356(0.014) 0.203(0.008) REV. A 04/11/2001 AT90S/LS2323/2343 62 10.16(0.400) 9.017(0.355) PIN ...

  • Page 63

    PIN 1 0 REF 8 1004D–09/01 .020 (.508) .012 (.305) .213 (5.41) .205 (5.21) .050 (1.27) BSC .212 (5.38) .203 (5.16) .013 (.330) .004 (.102) .010 (.254) .007 (.178) .035 (.889) .020 (.508) AT90S/LS2323/2343 .330 (8.38) .300 (7.62) .080 ...

  • Page 64

    ... Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...