at90ls8535-8mi

Manufacturer Part Numberat90ls8535-8mi
Description8-bit Microcontroller With 8k Bytes In-system Programmable Flash
ManufacturerATMEL Corporation
at90ls8535-8mi datasheet
 


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Features
®
AVR
– High-performance and Low-power RISC Architecture
– 118 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General-purpose Working Registers
– Up to 8 MIPS Throughput at 8 MHz
Data and Nonvolatile Program Memories
– 8K Bytes of In-System Programmable Flash
SPI Serial Interface for In-System Programming
Endurance: 1,000 Write/Erase Cycles
– 512 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 512 Bytes Internal SRAM
– Programming Lock for Software Security
Peripheral Features
– 8-channel, 10-bit ADC
– Programmable UART
– Master/Slave SPI Serial Interface
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare and
Capture Modes and Dual 8-, 9-, or 10-bit PWM
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– Power-on Reset Circuit
– Real-time Clock (RTC) with Separate Oscillator and Counter Mode
– External and Internal Interrupt Sources
– Three Sleep Modes: Idle, Power Save and Power-down
Power Consumption at 4 MHz, 3V, 20°C
– Active: 6.4 mA
– Idle Mode: 1.9 mA
– Power-down Mode: <1 µA
I/O and Packages
– 32 Programmable I/O Lines
– 40-lead PDIP, 44-lead PLCC, 44-lead TQFP, and 44-pad MLF
Operating Voltages
– V
: 4.0 - 6.0V AT90S8535
CC
– V
: 2.7 - 6.0V AT90LS8535
CC
Speed Grades:
– 0 - 8 MHz for the AT90S8535
– 0 - 4 MHz for the AT90LS8535
8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
AT90S8535
AT90LS8535
Rev. 1041H–11/01
1

at90ls8535-8mi Summary of contents

  • Page 1

    ... PDIP, 44-lead PLCC, 44-lead TQFP, and 44-pad MLF • Operating Voltages – 4.0 - 6.0V AT90S8535 CC – 2.7 - 6.0V AT90LS8535 CC • Speed Grades: – MHz for the AT90S8535 – MHz for the AT90LS8535 8-bit Microcontroller with 8K Bytes In-System Programmable Flash AT90S8535 AT90LS8535 Rev. 1041H–11/01 1 ...

  • Page 2

    Pin Configurations AT90S/LS8535 2 1041H–11/01 ...

  • Page 3

    Description Block Diagram 1041H–11/01 The AT90S8535 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S8535 achieves throughputs approaching 1 MIPS per MHz allowing the system designer ...

  • Page 4

    Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) AT90S/LS8535 4 The AVR core combines a rich instruction set with 32 general-purpose working regis- ters. All the 32 registers are directly connected to the Arithmetic Logic ...

  • Page 5

    Port D (PD7..PD0) RESET XTAL1 XTAL2 AVCC AREF AGND 1041H–11/01 current if the pull-up resistors are activated. Two Port C pins can alternatively be used as oscillator for Timer/Counter2. The Port C pins are tri-stated when a reset condition becomes ...

  • Page 6

    Clock Options Crystal Oscillator External Clock Timer Oscillator AT90S/LS8535 6 XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz ...

  • Page 7

    Architectural Overview 1041H–11/01 The fast-access register file concept contains 32 x 8-bit general-purpose working regis- ters with a single clock cycle access time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two ...

  • Page 8

    AT90S/LS8535 8 assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D ...

  • Page 9

    General-purpose Register File 1041H–11/01 memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority. Figure 6 shows the structure of the 32 general-purpose working registers in the ...

  • Page 10

    X-register, Y-register and Z- register ALU – Arithmetic Logic Unit In-System Programmable Flash Program Memory AT90S/LS8535 10 The registers R26..R31 have some added functions to their general-purpose usage. These registers are address pointers for indirect addressing of the Data Space. ...

  • Page 11

    SRAM Data Memory 1041H–11/01 Figure 8 shows how the AT90S8535 SRAM memory is organized. Figure 8. SRAM Organization Register File ... R29 R30 R31 I/O Registers $00 $01 $02 ... $3D $3E $3F The lower 608 data ...

  • Page 12

    Program and Data Addressing Modes Register Direct, Single Register Rd Register Direct, Two Registers Rd And Rr I/O Direct AT90S/LS8535 12 The AT90S8535 AVR RISC microcontroller supports powerful and efficient addressing modes for access to the program memory (Flash) and ...

  • Page 13

    Data Direct Data Indirect with Displacement Data Indirect 1041H–11/01 Figure 12. Direct Data Addressing LSBs 15 A 16-bit data address is contained in the 16 LSBs of a 2-word instruction. Rd/Rr specify the destination or ...

  • Page 14

    Data Indirect with Pre- decrement Data Indirect with Post- increment Constant Addressing Using the LPM Instruction AT90S/LS8535 14 Figure 15. Data Indirect Addressing with Pre-decrement REGISTER The X-, Y-, or the Z-register is decremented ...

  • Page 15

    Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL EEPROM Data Memory Memory Access Times and Instruction Execution Timing 1041H–11/01 Figure 18. Indirect Program Memory Addressing Program execution continues at address contained by the Z-register (i.e., the ...

  • Page 16

    AT90S/LS8535 16 Figure 20. The Parallel Instruction Fetches and Instruction Executions T1 System Clock Ø 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 21 shows the ...

  • Page 17

    I/O Memory 1041H–11/01 The I/O space definition of the AT90S8535 is shown in Table 1. Table 1. AT90S8535 I/O Space I/O Address (SRAM Address) Name $3F ($5F) SREG $3E ($5E) SPH $3D ($5D) SPL $3B ($5B) GIMSK $3A ($5A) GIFR ...

  • Page 18

    AT90S/LS8535 18 Table 1. AT90S8535 I/O Space (Continued) I/O Address (SRAM Address) Name Function $17 ($37) DDRB Data Direction Register, Port B $16 ($36) PINB Input Pins, Port B $15 ($35) PORTC Data Register, Port C $14 ($34) DDRC Data ...

  • Page 19

    Status Register – SREG 1041H–11/01 The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as: Bit $3F ($5F Read/Write R/W R/W R/W Initial Value • Bit 7 ...

  • Page 20

    Stack Pointer – SP Reset and Interrupt Handling AT90S/LS8535 20 The AT90S8535 Stack Pointer is implemented as two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S8535 data memory has $25F loca- tions, 10 ...

  • Page 21

    Reset Sources 1041H–11/01 Table 2. Reset and Interrupt Vectors (Continued) Vector No. Program Address 13 $00C 14 $00D 15 $00E 16 $00F 17 $010 The most typical and general program setup for the Reset and Interrupt vector addresses are: Address ...

  • Page 22

    Power-on Reset AT90S/LS8535 22 placed at these locations. The circuit diagram in Figure 23 shows the reset logic. Table 3 defines the timing and electrical parameters of the reset circuitry. Figure 23. Reset Logic Table 3. Reset Characteristics (V CC ...

  • Page 23

    External Reset 1041H–11/01 Figure 24. MCU Start-up, RESET Tied POT VCC V RST RESET t TOUT TIME-OUT INTERNAL RESET Figure 25. MCU Start-up, RESET Controlled Externally V POT VCC RESET TIME-OUT INTERNAL RESET An external reset is ...

  • Page 24

    Watchdog Reset MCU Status Register – MCUSR AT90S/LS8535 24 When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle dura- tion. On the falling edge of this pulse, the delay timer starts counting the ...

  • Page 25

    Interrupt Handling General Interrupt Mask Register – GIMSK 1041H–11/01 Table 6. Reset Source Identification EXTRF PORF The AT90S8535 has two 8-bit interrupt mask control registers: GIMSK (General Inter- rupt Mask register) and ...

  • Page 26

    General Interrupt Flag Register – GIFR Timer/Counter Interrupt Mask Register – TIMSK AT90S/LS8535 26 sponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bits 5.0 – Res: Reserved Bits These ...

  • Page 27

    Timer/Counter Interrupt Flag Register – TIFR 1041H–11/01 • Bit 5 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt ...

  • Page 28

    External Interrupts AT90S/LS8535 28 • Bit 5 – ICF1: Input Capture Flag 1 The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the Input Capture Register (ICR1). ICF1 ...

  • Page 29

    Interrupt Response Time MCU Control Register – MCUCR 1041H–11/01 The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. Four clock cycles after the interrupt flag has been set, the program vector address for the ...

  • Page 30

    Sleep Modes Idle Mode AT90S/LS8535 30 Table 8. Interrupt 1 Sense Control ISC11 ISC10 Description 0 0 The low level of INT1 generates an interrupt request Reserved 1 0 The falling edge of INT1 generates an interrupt request. ...

  • Page 31

    Power-down Mode Power Save Mode 1041H–11/01 Comparator Interrupt is not required, the Analog Comparator can be powered down by setting the ACD-bit in the Analog Comparator Control and Status Register (ACSR). This will reduce power consumption in Idle Mode. When ...

  • Page 32

    Timer/Counters Timer/Counter Prescalers AT90S/LS8535 32 The AT90S8535 provides three general-purpose Timer/Counters – two 8-bit T/Cs and one 16-bit T/C. Timer/Counter2 can optionally be asynchronously clocked from an exter- nal oscillator. This oscillator is optimized for use with a 32.768 kHz ...

  • Page 33

    Timer/Counter0 1041H–11/01 The clock source for Timer/Counter2 prescaler is named PCK2. PCK2 is by default con- nected to the main system clock (CK). By setting the AS2 bit in ASSR, Timer/Counter2 prescaler is asynchronously clocked from the PC6(TOSC1) pin. ...

  • Page 34

    Timer/Counter0 Control Register – TCCR0 Timer Counter 0 – TCNT0 AT90S/LS8535 34 Bit $33 ($53) – – – Read/Write Initial Value • Bits 7..3 – Res: Reserved Bits These bits are ...

  • Page 35

    Timer/Counter1 1041H–11/01 Figure 31 shows the block diagram for Timer/Counter1. Figure 31. Timer/Counter1 Block Diagram T/C1 COMPARE T/C1 OVER- FLOW IRQ MATCHA IRQ TIMER INT. MASK TIMER INT. FLAG REGISTER (TIMSK) REGISTER (TIFR T/C1 INPUT CAPTURE ...

  • Page 36

    Timer/Counter1 Control Register A – TCCR1A AT90S/LS8535 36 the counter on compareA match and actions on the Output Compare pins on both com- pare matches. Timer/Counter1 can also be used 10-bit Pulse Width Modulator. In ...

  • Page 37

    Timer/Counter1 Control Register B – TCCR1B 1041H–11/01 Table 11. Compare 1 Mode Select COM1X1 COM1X0 Description 0 0 Timer/Counter1 disconnected from output pin OC1X 0 1 Toggle the OC1X output line Clear the OC1X output line (to zero). ...

  • Page 38

    Timer/Counter1 – TCNT1H AND TCNT1L AT90S/LS8535 38 • Bit 3 – CTC1: Clear Timer/Counter1 on Compare Match When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compareA match. If ...

  • Page 39

    Timer/Counter1 Output Compare Register – OCR1AH AND OCR1AL Timer/Counter1 Output Compare Register – OCR1BH AND OCR1BL 1041H–11/01 TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt routines). ...

  • Page 40

    Timer/Counter1 Input Capture Register – ICR1H AND ICR1L Timer/Counter1 In PWM Mode AT90S/LS8535 40 OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a ...

  • Page 41

    When the prescaler is in use (CS12..CS10 ≠ 001 or 000), the PWM output goes active when the counter reaches TOP value, but the down-counting compare match is not interpreted to be ...

  • Page 42

    Timer/Counter2 AT90S/LS8535 42 Table 16. PWM Outputs OCR1X = $0000 or TOP COM1X1 COM1X0 Note PWM mode, the Timer Overflow Flag1 (TOV1) is set when the counter advances from ...

  • Page 43

    Timer/Counter2 Control Register – TCCR2 1041H–11/01 Timer/Counter Control Register (TCCR2). The interrupt enable/disable settings are found in the Timer/Counter Interrupt Mask Register (TIMSK). This module features a high-resolution and a high-accuracy usage with the lower pres- caling opportunities. Similarly, the ...

  • Page 44

    Timer/Counter2 – TCNT2 Timer/Counter2 Output Compare Register – OCR2 AT90S/LS8535 44 When the prescaler is set to divide by 8, the timer will count like this: ... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, ...

  • Page 45

    Timer/Counter2 in PWM Mode 1041H–11/01 When the PWM mode is selected, Timer/Counter2 and the Output Compare Register (OCR2) form an 8-bit, free-running, glitch-free and phase correct PWM with outputs on the PD7(OC2) pin. Timer/Counter2 acts as an up/down counter, counting ...

  • Page 46

    Asynchronous Status Register – ASSR AT90S/LS8535 46 Table 20. PWM Outputs OCR2 = $00 or $FF COM21 COM20 PWM mode, the Timer Overflow Flag (TOV2) is set when the counter advances from $00. ...

  • Page 47

    Asynchronous Operation of Timer/Counter2 1041H–11/01 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the timer registers TCNT2, OCR2 and TCCR2 might get corrupted. A safe procedure for switching ...

  • Page 48

    AT90S/LS8535 48 least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. • During asynchronous operation, the synchronization ...

  • Page 49

    Watchdog Timer Watchdog Timer Control Register – WDTCR 1041H–11/01 The Watchdog Timer is clocked from a separate On-chip oscillator. By controlling the Watchdog Timer prescaler, the Watchdog reset interval can be adjusted as shown in Table 21. See characterization data ...

  • Page 50

    AT90S/LS8535 the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must be written to WDE even though it is set to “1” before the disable operation starts. 2. Within the next four ...

  • Page 51

    EEPROM Read/Write Access EEPROM Address Register – EEARH and EEARL EEPROM Data Register – EEDR EEPROM Control Register – EECR 1041H–11/01 The EEPROM access registers are accessible in the I/O space. The write access time is in the range of ...

  • Page 52

    AT90S/LS8535 52 • Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to “1” causes the EEPROM to be written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at ...

  • Page 53

    Prevent EEPROM Corruption 1041H–11/01 During periods of low V , the EEPROM data can be corrupted because the supply volt- CC age is too low for the CPU and the EEPROM to operate properly. These issues are the same as ...

  • Page 54

    Serial Peripheral Interface – SPI AT90S/LS8535 54 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90S8535 and peripheral devices or between several AVR devices. The AT90S8535 SPI features include the following: • Full-duplex, 3-wire Synchronous Data ...

  • Page 55

    Figure 38. SPI Master-slave Interconnection MSB MASTER LSB 8 BIT SHIFT REGISTER SPI CLOCK GENERATOR The system is single-buffered in the transmit direction and double-buffered in the receive direction. This means that bytes to be transmitted cannot be written ...

  • Page 56

    SS Pin Functionality Data Modes AT90S/LS8535 56 When the SPI is configured as a master (MSTR in SPCR is set), the user can determine the direction of the SS pin configured as an output, the pin is ...

  • Page 57

    SPI Control Register – SPCR 1041H–11/01 Figure 40. SPI Transfer Format with CPHA = 1 and DORD = 0 Bit $0D ($2D) SPIE SPE DORD Read/Write R/W R/W R/W Initial Value • Bit 7 ...

  • Page 58

    SPI Status Register – SPSR SPI Data Register – SPDR AT90S/LS8535 58 • Bits 1,0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a master. SPR1 ...

  • Page 59

    UART Data Transmission 1041H–11/01 The AT90S8535 features a full duplex (separate receive and transmit registers) Univer- sal Asynchronous Receiver and Transmitter (UART). The main features are: • Baud Rate Generator that can Generate a Large Number of Baud Rates (bps) ...

  • Page 60

    Data Reception AT90S/LS8535 60 is selected (the CHR9 bit in the UART Control Register, UCR is set), the TXB8 bit in UCR is transferred to bit 9 in the Transmit shift register. On the baud rate clock following the transfer ...

  • Page 61

    Following the 1-to-0 transition, the receiver samples the RXD pin at samples 8, 9 and 10. If two or more of these three samples are found to be logical “1”s, the start bit is ...

  • Page 62

    UART Control UART I/O Data Register – UDR UART Status Register – USR AT90S/LS8535 62 Bit $0C ($2C) MSB Read/Write R/W R/W R/W Initial Value The UDR register is actually two physically separate registers ...

  • Page 63

    UART Control Register – UCR 1041H–11/01 The FE bit is cleared when the stop bit of received data is one. • Bit 3 – OR: OverRun This bit is set if an Overrun condition is detected, i.e., when a character ...

  • Page 64

    Baud Rate Generator AT90S/LS8535 64 The baud rate generator is a frequency divider which generates baud rates according to the following equation: BAUD • BAUD = Baud rate • Crystal clock frequency CK • UBRR = Contents of ...

  • Page 65

    UART Baud Rate Register – UBRR 1041H–11/01 Bit $09 ($29) MSB Read/Write R/W R/W R/W Initial Value The UBRR register is an 8-bit read/write register that specifies the UART Baud Rate according to the ...

  • Page 66

    Analog Comparator Analog Comparator Control and Status Register – ACSR AT90S/LS8535 66 The Analog Comparator compares the input values on the positive input PB2 (AIN0) and negative input PB3 (AIN1). When the voltage on the positive input PB2 (AIN0) is ...

  • Page 67

    Bit 2 – ACIC: Analog Comparator Input Capture Enable When set (one), this bit enables the Input Capture function in Timer/Counter1 to be trig- gered by the Analog Comparator. The comparator output is in this case directly connected ...

  • Page 68

    Analog-to-Digital Converter Feature list AT90S/LS8535 68 • 10-bit Resolution • 0.5 LSB Integral Non-linearity • ±2 LSB Absolute Accuracy • 260 µs Conversion Time • kSPS at Maximum Resolution • 8 Multiplexed Input Channels • ...

  • Page 69

    Operation Prescaling 1041H–11/01 The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents AGND and the maximum value repre- sents the voltage on the AREF pin minus one LSB. The analog ...

  • Page 70

    AT90S/LS8535 70 higher sampling rate. See “ADC Characteristics” on page 75 for more details. The ADC module contains a prescaler, which divides the system clock to an acceptable ADC clock frequency. The ADPS2..0 bits in ADCSR are used to generate ...

  • Page 71

    ADC Noise Canceler Function 1041H–11/01 Figure 48. ADC Timing Diagram, Single Conversion Cycle number ADC clock ADSC ADIF ADCH ADCL Sample & hold MUX and REFS update Figure 49. ADC Timing Diagram, Free Running Conversion ...

  • Page 72

    ADC Multiplexer Select Register – ADMUX ADC Control and Status Register – ADCSR AT90S/LS8535 72 2. Enter Idle Mode. The ADC will start a conversion once the CPU has been halted other interrupts occur before the ADC ...

  • Page 73

    ADC Data Register – ADCL AND ADCH 1041H–11/01 ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a extended conversion precedes a real conversion, ADSC will ...

  • Page 74

    Scanning Multiple Channels ADC Noise Canceling Techniques AT90S/LS8535 74 • ADC9..0: ADC Conversion result These bits represent the result from the conversion. $000 represents analog ground and $3FF represents the selected reference voltage minus one LSB. Since change of analog ...

  • Page 75

    ADC Characteristics = -40 ° ° Symbol Parameter Resolution Absolute accuracy Absolute accuracy Absolute accuracy Integral Non-linearity Differential Non-linearity Zero Error (Offset) Conversion Time Clock Frequency AV Analog Supply Voltage CC V Reference Voltage ...

  • Page 76

    I/O Ports Port A Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA AT90S/LS8535 76 All AVR ports have true read-modify-write functionality when used as general digital I/O ports. ...

  • Page 77

    Port A as General Digital I/O Port A Schematics 1041H–11/01 All eight pins in Port A have equal functionality when used as digital I/O pins. PAn, general I/O pin: The DDAn bit in the DDRA register selects the direction of ...

  • Page 78

    Port B Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB AT90S/LS8535 78 Port 8-bit bi-directional I/O port. Three I/O memory address locations are allocated for ...

  • Page 79

    Port B As General Digital I/O Alternate Functions of Port B 1041H–11/01 All eight pins in Port B have equal functionality when used as digital I/O pins. PBn, general I/O pin: The DDBn bit in the DDRB register selects the ...

  • Page 80

    Port B Schematics AT90S/LS8535 80 allows analog signals that are close to V causing excessive power consumption. • AIN0 – Port B, Bit 2 AIN0, Analog Comparator Positive Input. When configured as an input (DDB2 is cleared [zero]) and with ...

  • Page 81

    Figure 53. Port B Schematic Diagram (Pins PB2 and PB3) MOS PULL- UP PBn PWRDN WP: WRITE PORTB WD: WRITE DDRB RL: READ PORTB LATCH RP: READ PORTB PIN RD: READ DDRB Figure ...

  • Page 82

    AT90S/LS8535 82 Figure 55. Port B Schematic Diagram (Pin PB5) MOS PULL- UP PB5 WP: WRITE PORTB WRITE DDRB WD: READ PORTB LATCH RL: RP: READ PORTB PIN RD: READ DDRB SPE: SPI ENABLE MASTER SELECT MSTR Figure 56. Port ...

  • Page 83

    Figure 57. Port B Schematic Diagram (Pin PB7) MOS PULL- UP PB7 WP: WRITE PORTB WRITE DDRB WD: READ PORTB LATCH RL: READ PORTB PIN RP: READ DDRB RD: SPI ENABLE SPE: MASTER SELECT MSTR AT90S/LS8535 RD RESET R ...

  • Page 84

    Port C Port C Data Register – PORTC Port C Data Direction Register – DDRC Port C Input Pins Address – PINC Port C As General Digital I/O AT90S/LS8535 84 Port 8-bit bi-directional I/O port. Three I/O ...

  • Page 85

    Alternate Functions of Port C Port C Schematics 1041H–11/01 When the AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter2, pins PC6 and PC7 are disconnected from the port. In this mode, a crystal oscillator is ...

  • Page 86

    Port D AT90S/LS8535 86 Figure 60. Port C Schematic Diagram (Pins PC7) Port 8-bit bi-directional I/O port with internal pull-up resistors. Three I/O memory address locations are allocated for Port D, one each for the Data Register ...

  • Page 87

    Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port D As General Digital I/O Alternate Functions of Port D 1041H–11/01 Bit $12 ($32) PORTD7 PORTD6 ...

  • Page 88

    AT90S/LS8535 88 • OC1A – Port D, Bit 5 OC1A, Output compare matchA output: The PD5 pin can serve as an external output for the Timer/Counter1 output compareA. The pin has to be configured as an output (DDD5 set [one]) ...

  • Page 89

    Port D Schematics 1041H–11/01 Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 61. Port D Schematic Diagram (Pin PD0) MOS PULL- UP PD0 WP: WRITE PORTD WD: WRITE DDRD RL: ...

  • Page 90

    AT90S/LS8535 90 Figure 63. Port D Schematic Diagram (Pins PD2 and PD3) Figure 64. Port D Schematic Diagram (Pins PD4 and PD5) 1041H–11/01 ...

  • Page 91

    Figure 65. Port D Schematic Diagram (Pin PD6) MOS PULL- UP PD6 WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ DDRD ACIC: COMPARATOR IC ENABLE ACO: COMPARATOR OUTPUT Figure 66. Port ...

  • Page 92

    Memory Programming Program and Data Memory Lock Bits Fuse Bits Signature Bytes Programming the Flash and EEPROM AT90S/LS8535 92 The AT90S8535 MCU provides two Lock bits that can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the ...

  • Page 93

    ... Table 36. Supply Voltage during Programming Part Serial Programming AT90S8535 4.0 - 6.0V AT90LS8535 2.7 - 6.0V This section describes how to parallel program and verify Flash program memory, EEPROM data memory, Lock bits and Fuse bits in the AT90S8535. In this section, some pins of the AT90S8535 are referenced by signal names describing their function during parallel programming ...

  • Page 94

    Enter Programming Mode AT90S/LS8535 94 Table 37. Pin Name Mapping Signal Name in Programming Mode Pin Name RDY/BSY PD1 OE PD2 WR PD3 BS PD4 XA0 PD5 XA1 PD6 DATA PB7 - 0 Table 38. XA1 and XA0 Coding XA1 ...

  • Page 95

    Chip Erase Programming the Flash 1041H–11/01 The Chip Erase command will erase the Flash and EEPROM memories and the Lock bits. The Lock bits are not reset until the Flash and EEPROM have been completely erased. The Fuse bits are ...

  • Page 96

    AT90S/LS8535 96 1. Set BS to “1”. This selects high data. 2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low. 3. Wait until RDY/BSY goes high to program the next byte. (See Figure ...

  • Page 97

    Reading the Flash Programming the EEPROM Reading the EEPROM 1041H–11/01 Figure 69. Programming the Flash Waveforms (Continued) DATA DATA HIGH XA1 XA0 BS XTAL1 WR RDY/BSY RESET +12V OE The algorithm for reading the Flash memory is as follows (refer ...

  • Page 98

    Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes AT90S/LS8535 98 The algorithm for programming the Fuse bits is as follows (refer to “Programming the Flash” for details on command and ...

  • Page 99

    Parallel Programming Characteristics Serial Downloading 1041H–11/01 Figure 70. Parallel Programming Timing t XTAL1 XHXL t DVXH Data & Contol (DATA, XA0/1, BS) WR RDY/BSY OE DATA Table 40. Parallel Programming Characteristics, T Symbol Parameter V Programming Enable Voltage PP I ...

  • Page 100

    Serial Programming Algorithm AT90S/LS8535 100 Figure 71. Serial Programming and Verify GND CLOCK INPUT For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction and there is no need to first execute the Chip Erase instruction. The ...

  • Page 101

    Data Polling EEPROM Data Polling Flash 1041H–11/ Chip Erase is performed (must be done to erase the Flash), wait t after the instruction, give RESET a positive pulse and start over from step 2. See Table 44 ...

  • Page 102

    Table 42. Serial Programming Instruction Set Instruction Byte 1 1010 1100 Programming Enable 1010 1100 Chip Erase 0010 H000 Read Program Memory 0100 H000 Write Program Memory 1010 0000 Read EEPROM Memory 1100 0000 Write EEPROM Memory 0101 1000 Read ...

  • Page 103

    Serial Programming Characteristics 1041H–11/01 Figure 73. Serial Programming Timing MOSI t OVSH SCK MISO Table 43. Serial Programming Characteristics, T (unless otherwise noted) Symbol Parameter 1/t Oscillator Frequency (V CLCL t Oscillator Period (V = 2.7 - 4.0V) CLCL CC ...

  • Page 104

    Electrical Characteristics Absolute Maximum Ratings* Operating Temperature ................................ -40°C to +105°C Storage Temperature .................................... -65°C to +150°C Voltage on Any Pin except RESET with Respect to Ground .............................-1. Voltage on RESET with Respect to Ground ....-1.0V to +13.0V ...

  • Page 105

    DC Characteristics (Continued) = -40 ° ° 2.7V to 6.0V (unless otherwise noted Symbol Parameter Analog Comparator Input V ACIO Offset Voltage Analog Comparator Input I ACLK Leakage A Analog Comparator ...

  • Page 106

    External Clock Drive Waveforms AT90S/LS8535 106 Figure 74. External Clock VIH1 VIL1 Table 46. External Clock Drive Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t ...

  • Page 107

    Typical Characteristics 1041H–11/01 The following charts show typical behavior. These figures are not tested during manu- facturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with ...

  • Page 108

    AT90S/LS8535 108 Figure 76. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs 2.5 3 3.5 Figure 77. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY 20 ...

  • Page 109

    Figure 78. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs 2.5 3 Figure 79. Power-down Supply Current vs. V POWER DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER DISABLED ...

  • Page 110

    AT90S/LS8535 110 Figure 80. Power-down Supply Current vs. V POWER DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 140 120 100 2.5 3 3.5 Figure 81. Power Save Supply Current vs. V POWER SAVE ...

  • Page 111

    Figure 82. Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT vs 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 2.5 3 Note: Analog comparator offset voltage is measured as absolute offset. Figure 83. Analog ...

  • Page 112

    AT90S/LS8535 112 Figure 84. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE 0.5 1 Common Mode Voltage (V) Figure 85. Analog Comparator Input Leakage Current ...

  • Page 113

    Figure 86. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V 1600 1400 1200 1000 800 600 400 200 0 2 2.5 3 Note: Sink and source capabilities of I/O ports are measured on one pin at a ...

  • Page 114

    AT90S/LS8535 114 Figure 88. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE ˚ ˚ 0.5 1 Figure 89. ...

  • Page 115

    Figure 90. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE ˚ ˚ ...

  • Page 116

    AT90S/LS8535 116 Figure 92. I/O Pin Source Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 Figure 93. I/O Pin Input Threshold Voltage vs. V I/O PIN INPUT THRESHOLD VOLTAGE ...

  • Page 117

    Figure 94. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 AT90S/LS8535 ˚ 5.0 117 ...

  • Page 118

    Register Summary Address Name Bit 7 $3F ($5F) SREG I $3E ($5E) SPH - $3D ($5D) SPL SP7 $3C ($5C) Reserved $3B ($5B) GIMSK INT1 $3A ($5A) GIFR INTF1 $39 ($59) TIMSK OCIE2 $38 ($58) TIFR OCF2 $37 ($57) Reserved ...

  • Page 119

    Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the status flags are cleared by writing a logical “1” to them. Note ...

  • Page 120

    Instruction Set Summary Mnemonic Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add Two Registers ADC Rd, Rr Add with Carry Two Registers ADIW Rdl, K Add Immediate to Word SUB Rd, Rr Subtract Two Registers SUBI Rd, K ...

  • Page 121

    Instruction Set Summary (Continued) Mnemonic Operands Description LD Rd, Y Load Indirect LD Rd, Y+ Load Indirect and Post-inc. LD Rd, -Y Load Indirect and Pre-dec. LDD Rd, Y+q Load Indirect with Displacement LD Rd, Z Load Indirect LD Rd, ...

  • Page 122

    ... AT90LS8535-4MI 44M1 AT90S8535-8AC 44A AT90S8535-8JC 44J AT90S8535-8PC 40P6 AT90LS8535-8MC 44M1 AT90S8535-8AI 44A AT90S8535-8JI 44J AT90S8535-8PI 40P6 AT90LS8535-8MI 44M1 Package Type Operation Range Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Commercial (0°C to 70°C) Industrial (-40°C to 85°C) 1041H–11/01 ...

  • Page 123

    Packaging Information 44A 44-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP), 10x10mm body, 2.0mm footprint, 0.8mm pitch. Dimension in Millimeters and (Inches)* JEDEC STANDARD MS-026 ACB 0.80(0.0315) BSC 0.20(0.008) 0.09(0.004) REV. A 04/11/2001 1041H–11/01 PIN 1 ID PIN 1 0˚~7˚ ...

  • Page 124

    Plastic J-leaded Chip Carrier (PLCC) Dimensions in Milimeters and (Inches)* JEDEC STANDARD MS-018 AC 1.14(0.045) X 45˚ 0.813(0.032) 0.660(0.026) 1.27(0.050) TYP REV. A 04/11/2001 AT90S/LS8535 124 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFY 16.70(0.656) SQ 16.50(0.650) 17.70(0.695) ...

  • Page 125

    Plastic Dual Inline Parkage (PDIP), 0.600" wide Demension in Millimeters and (Inches)* JEDEC STANDARD MS-011 AC 4.83(0.190)MAX SEATING PLANE 3.56(0.140) 3.05(0.120) 2.54(0.100)BSC 0.38(0.015) 0.20(0.008) REV. A 04/11/2001 1041H–11/01 52.71(2.075) 51.94(2.045) 48.26(1.900) REF 1.65(0.065) 1.27(0.050) 15.88(0.625) 15.24(0.600) 0º ~ ...

  • Page 126

    NOTE 1. JEDEC STANDARD MO-220, Fig 1 (Saw Singulation), VKKD-1 AT90S/LS8535 126 D Marked pin#1 identifier E TOP VIEW L PIN #1 CORNER BOTTOM VIEW TITLE 2325 Orchard Parkway 44M1, 44-pad , ...

  • Page 127

    ... Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...