at90ls8535-8mi ATMEL Corporation, at90ls8535-8mi Datasheet - Page 29

• Manufacturer Part Number: at90ls8535-8mi
• Description: 8-bit Microcontroller With 8k Bytes In-system Programmable Flash
• Manufacturer: ATMEL Corporation

Interrupt Response Time
MCU Control Register –
MCUCR
1041H–11/01
The interrupt execution response for all the enabled AVR interrupts is four clock cycles
minimum. Four clock cycles after the interrupt flag has been set, the program vector
address for the actual interrupt handling routine is executed. During this 4-clock-cycle
period, the Program Counter (2 bytes) is pushed onto the stack and the Stack Pointer is
decremented by 2. The vector is normally a relative jump to the interrupt routine and this
jump takes two clock cycles. If an interrupt occurs during execution of a multi-cycle
instruction, this instruction is completed before the interrupt is served.
A return from an interrupt handling routine (same as for a subroutine call routine) takes
four clock cycles. During these four clock cycles, the Program Counter (2 bytes) is
popped back from the stack, the Stack Pointer is incremented by 2 and the I-flag in
SREG is set. When the AVR exits from an interrupt, it will always return to the main pro-
gram and execute one more instruction before any pending interrupt is served.
The MCU Control Register contains control bits for general MCU functions.
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the AT90S8535 and always reads zero.
• Bit 6 – SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the Sleep Mode when the SLEEP
instruction is executed. To avoid the MCU entering the Sleep Mode unless it is the pro-
grammer’s purpose, it is recommended to set the Sleep Enable (SE) bit just before the
execution of the SLEEP instruction.
• Bits 5, 4 – SM1/SM0: Sleep Mode Select Bits 1 and 0
These bits select between the three available sleep modes as shown in Table 7.
Table 7. Sleep Mode Select
• Bits 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bits 1 and 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the
corresponding interrupt mask in the GIMSK is set. The level and edges on the external
INT1 pin that activate the interrupt are defined in Table 8.
Bit
$35 ($55)
Read/Write
Initial Value
SM1
0
0
1
1
R
7
–
0
R/W
SE
6
0
SM0
SM1
R/W
0
1
0
1
5
0
SM0
R/W
4
0
Sleep Mode
Idle
Reserved
Power-down
Power Save
ISC11
R/W
3
0
ISC10
R/W
2
0
AT90S/LS8535
ISC01
R/W
1
0
ISC00
R/W
0
0
MCUCR
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