at90ls8535-8mi ATMEL Corporation, at90ls8535-8mi Datasheet - Page 31

• Manufacturer Part Number: at90ls8535-8mi
• Description: 8-bit Microcontroller With 8k Bytes In-system Programmable Flash
• Manufacturer: ATMEL Corporation

Power-down Mode
Power Save Mode
1041H–11/01
Comparator Interrupt is not required, the Analog Comparator can be powered down by
setting the ACD-bit in the Analog Comparator Control and Status Register (ACSR). This
will reduce power consumption in Idle Mode. When the MCU wakes up from Idle Mode,
the CPU starts program execution immediately.
When the SM1/SM0 bits are set to 10, the SLEEP instruction makes the MCU enter the
Power-down mode. In this mode, the external oscillator is stopped while the external
interrupts and the Watchdog (if enabled) continue operating. Only an external reset, a
Watchdog reset (if enabled) or an external level interrupt can wake up the MCU.
Note that when a level-triggered interrupt is used for wake-up from power-down, the low
level must be held for a time longer than the reset delay Time-out period t
When waking up from Power-down mode, a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable
after having been stopped. The wake-up period is equal to the reset period, as shown in
Table 3 on page 22.
If the wake-up condition disappears before the MCU wakes up and starts to execute,
e.g., a low-level on is not held long enough, the interrupt causing the wake-up will not be
executed.
When the SM1/SM0 bits are 11, the SLEEP instruction makes the MCU enter the Power
Save Mode. This mode is identical to Power -down, with one exception: If
Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set,
Timer/Counter2 will run during sleep. In addition to the power-down wake-up sources,
the device can also wake up from either a Timer Overflow or Output Compare event
from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in
TIMSK and the global interrupt enable bit in SREG is set.
When waking up from Power Save Mode by an external interrupt, two instruction cycles
are executed before the interrupt flags are updated. When waking up by the asynchro-
nous timer, three instruction cycles are executed before the flags are updated. During
these cycles, the processor executes instructions, but the interrupt condition is not read-
able and the interrupt routine has not started yet.
When waking up from Power Save Mode by an asynchronous timer interrupt, the part
will wake up even if global interrupts are disabled. To ensure that the part executes the
interrupt routine when waking up, also set the global interrupt enable bit in SREG.
If the asynchronous timer is not clocked asynchronously, Power-down mode is recom-
mended instead of Power Save Mode because the contents of the registers in the
asynchronous timer should be considered undefined after wake-up in Power Save
Mode, even if AS2 is 0.
AT90S/LS8535
TOUT
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