at90usb647-16au

Manufacturer Part Numberat90usb647-16au
DescriptionAt90usb1286 8-bit Avr Microcontroller With 64/128k Bytes Of Isp Flash And Usb Controller
ManufacturerATMEL Corporation
at90usb647-16au datasheet
 
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Features
High Performance, Low Power AVR
Advanced RISC Architecture
– 135 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-Chip 2-cycle Multiplier
Non-volatile Program and Data Memories
– 64/128K Bytes of In-System Self-Programmable Flash
• Endurance: 100,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
• USB Bootloader programmed by default in the Factory
• In-System Programming by On-chip Boot Program hardware activated after
reset
• True Read-While-Write Operation
• All supplied parts are preprogramed with a default USB bootloader
– 2K/4K (64K/128K Flash version) Bytes EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 4K/8K (64K/128K Flash version) Bytes Internal SRAM
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
JTAG (IEEE std. 1149.1 compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
USB 2.0 Full-speed/Low-speed Device and On-The-Go Module
– Complies fully with:
– Universal Serial Bus Specification REV 2.0
– On-The-Go Supplement to the USB 2.0 Specification Rev 1.0
– Supports data transfer rates up to 12 Mbit/s and 1.5 Mbit/s
USB Full-speed/Low Speed Device Module with Interrupt on Transfer Completion
– Endpoint 0 for Control Transfers : up to 64-bytes
– 6 Programmable Endpoints with IN or Out Directions and with Bulk, Interrupt or
Isochronous Transfers
– Configurable Endpoints size up to 256 bytes in double bank mode
– Fully independant 832 bytes USB DPRAM for endpoint memory allocation
– Suspend/Resume Interrupts
– Power-on Reset and USB Bus Reset
– 48 MHz PLL for Full-speed Bus Operation
– USB Bus Disconnection on Microcontroller Request
USB OTG Reduced Host :
– Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
for OTG dual-role devices
– Provide Status and control signals for software implementation of HNP and SRP
– Provides programmable times required for HNP and SRP
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– Two16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode
®
8-Bit Microcontroller
8-bit
Microcontroller
with
64/128K Bytes
of ISP Flash
and USB
Controller
AT90USB646
AT90USB647
AT90USB1286
AT90USB1287
Summary
7593GS–AVR–03/08

at90usb647-16au Summary of contents

  • Page 1

    ... Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – Two16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode ® 8-Bit Microcontroller 8-bit Microcontroller with 64/128K Bytes of ISP Flash and USB Controller AT90USB646 AT90USB647 AT90USB1286 AT90USB1287 Summary 7593GS–AVR–03/08 ...

  • Page 2

    Real Time Counter with Separate Oscillator – Four 8-bit PWM Channels – Six PWM Channels with Programmable Resolution from Bits – Output Compare Modulator – 8-channels, 10-bit ADC – Programmable Serial USART – Master/Slave SPI Serial ...

  • Page 3

    Pin Configurations Figure 1-1. 1 (INT.6/AIN.0) PE6 2 (INT.7/AIN.1/UVcon) PE7 3 UVcc UGnd 7 UCap 8 VBus 9 (IUID) PE3 10 (SS/PCINT0) PB0 11 (PCINT1/SCLK) PB1 12 (PDI/PCINT2/MOSI) PB2 13 (PDO/PCINT3/MISO) PB3 14 (PCINT4/OC.2A) ...

  • Page 4

    Figure 1-2. (INT.6/AIN.0) PE6 (INT.7/AIN.1/UVcon) PE7 (SS/PCINT0) PB0 (PCINT1/SCLK) PB1 (PDI/PCINT2/MOSI) PB2 (PDO/PCINT3/MISO) PB3 (PCINT4/OC.2A) PB4 (PCINT5/OC.1A) PB5 (PCINT6/OC.1B) PB6 Note: 1.1 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured ...

  • Page 5

    AT90USB64/128 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram PF7 - PF0 VCC PORTF DRIVERS GND DATA REGISTER PORTF AVCC ADC AGND AREF ...

  • Page 6

    The AT90USB64/128 provides the following features: 64/128K bytes of In-System Programma- ble Flash with Read-While-Write capabilities, 2K/4K bytes EEPROM, 4K/8K bytes SRAM, 48 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with ...

  • Page 7

    Port B (PB7..PB0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B ...

  • Page 8

    D- USB Full speed / Low Speed Negative Data Upstream Port. Should be connected to the USB D- connector pin with a serial 22 Ohms resistor. 2.2.10 D+ USB Full speed / Low Speed Positive Data Upstream Port. Should ...

  • Page 9

    I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". 7593GS–AVR–03/08 AT90USB64/128 9 ...

  • Page 10

    Register Summary Address Name Bit 7 (0xFF) Reserved - (0xFE) Reserved - (0xFD) Reserved - (0xFC) Reserved - - (0xFB) Reserved (0xFA) Reserved - (0xF9) OTGTCON (0xF8) UPINT (0xF7) UPBCHX - (0xF6) UPBCLX (0xF5) UPERRX - (0xF4) UEINT (0xF3) ...

  • Page 11

    Address Name Bit 7 (0xBE) Reserved - (0xBD) TWAMR TWAM6 (0xBC) TWCR TWINT (0xBB) TWDR (0xBA) TWAR TWA6 (0xB9) TWSR TWS7 (0xB8) TWBR (0xB7) Reserved - (0xB6) ASSR - (0xB5) Reserved - (0xB4) OCR2B (0xB3) OCR2A (0xB2) TCNT2 (0xB1) TCCR2B ...

  • Page 12

    Address Name Bit 7 (0x7C) ADMUX REFS1 (0x7B) ADCSRB ADHSM (0x7A) ADCSRA ADEN (0x79) ADCH (0x78) ADCL (0x77) Reserved - (0x76) Reserved - (0x75) XMCRB XMBK (0x74) XMCRA SRE (0x73) Reserved - (0x72) Reserved - (0x71) TIMSK3 - (0x70) TIMSK2 ...

  • Page 13

    Address Name Bit 7 0x1B (0x3B) PCIFR - 0x1A (0x3A) Reserved - 0x19 (0x39) Reserved - 0x18 (0x38) TIFR3 - 0x17 (0x37) TIFR2 - 0x16 (0x36) TIFR1 - 0x15 (0x35) TIFR0 - 0x14 (0x34) Reserved - 0x13 (0x33) Reserved - ...

  • Page 14

    Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr ADC Rd, Rr ADIW Rdl,K SUB Rd, Rr SUBI Rd, K SBC Rd, Rr SBCI Rd, K SBIW Rdl,K AND Rd, Rr ANDI Rd Rd, ...

  • Page 15

    Mnemonics Operands BRVC k BRIE k BRID k BIT AND BIT-TEST INSTRUCTIONS SBI P,b CBI P,b LSL Rd LSR Rd ROL Rd ROR Rd ASR Rd SWAP Rd BSET s BCLR s BST Rr, b BLD Rd, b SEC CLC ...

  • Page 16

    Mnemonics Operands SPM IN Rd, P OUT P, Rr PUSH Rr POP Rd MCU CONTROL INSTRUCTIONS NOP SLEEP WDR BREAK AT90USB64/128 16 Description Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack No Operation ...

  • Page 17

    ... AT OTG AT90USB1287-16MU OTG Device 90USB1286-16MU AT only 90USB647-16AU AT OTG AT90USB647-16MU OTG Device 90USB646-16MU AT only Lead, 14x14 mm Body Size, 1.0mm Body Thickness 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP Lead, 9x9 mm Body Size, 0.50mm Pitch Quad Flat No Lead Package (QFN) 7593GS– ...

  • Page 18

    TQFP64 AT90USB64/128 18 7593GS–AVR–03/08 ...

  • Page 19

    AT90USB64/128 19 ...

  • Page 20

    QFN64 AT90USB64/128 20 7593GS–AVR–03/08 ...

  • Page 21

    AT90USB64/128 21 ...

  • Page 22

    Errata 8. AT90USB1287/6 Errata. AT90USB1287/6 8.1 Errata History Silicon 90USB1286-16MU Release First Release Date Code up to 0648 Date Code from 0709 to 0801 Second Release except lots 0801 7H5103* Lots 0801 7H5103* and Third Release Date Code from ...

  • Page 23

    The VSession valid threshold voltage is internally connected to VBus_Valid (4.4V approx.). That causes the device to attach to the bus only when Vbus is greater than VBusValid instead of V_Session Valid. Thus if VBUS is lower than 4.4V, the ...

  • Page 24

    AT90USB1287/6 Second Release • USB Eye Diagram violation in low-speed mode • Transient perturbation in USB suspend mode generates over consumption • VBUS Session valid threshold voltage • Spike on TWI pins when TWI is enabled • High current ...

  • Page 25

    Problem Fix/workaround Before entering sleep, interrupts not used to wake up the part from the sleep mode should be disabled. 1. Asynchronous timer interrupt wake up from sleep generates multiple interrupts If the CPU core is in sleep and wakes-up ...

  • Page 26

    AT90USB1287/6 Third Release • Transient perturbation in USB suspend mode generates over consumption • Spike on TWI pins when TWI is enabled • High current consumption in sleep mode • Async timer interrupt wake up from sleep generate multiple ...

  • Page 27

    ... Problem Fix/workaround A software workaround is to wait beforeperforming the sleep instruction: until TCNT2>OCR2+1. 9. AT90USB647/6 Errata. • USB Eye Diagram violation in low-speed mode • Transient perturbation in USB suspend mode generates over consumption • Spike on TWI pins when TWI is enabled • High current consumption in sleep mode • ...

  • Page 28

    If the CPU core is in sleep and wakes-up from an asynchronous timer interrupt and then go back in sleep mode again it may wake up several times. Problem Fix/workaround ...

  • Page 29

    Datasheet Revision History for AT90USB64/128 Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 10.1 Changes from 7593A to 7593B 1. ...

  • Page 30

    ... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2007 Atmel Corporation. All rights reserved. Atmel Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia ...