at91sam7l128 ATMEL Corporation, at91sam7l128 Datasheet
at91sam7l128
Available stocks
Related parts for at91sam7l128
at91sam7l128 Summary of contents
Page 1
... In-circuit Emulation, Debug Communication Channel Support • Internal High-speed Flash – 128 Kbytes (AT91SAM7L128), Organized in 512 Pages of 256 Bytes Single Plane – 64 Kbytes (AT91SAM7L64), Organized In 256 Pages of 256 Bytes Single Plane – Single Cycle Access MHz in Worst Case Conditions – ...
Page 2
... Embedded 1.8V Regulator, Drawing for the Core with Programmable Output Voltage – Single Supply 1.8V - 3.6V • Fully Static Operation MHz at 85°C, Worst Case Conditions • Available in a 128-lead LQFP Green and a 144-ball LFBGA Green Package AT91SAM7L128/64 Preliminary 2 ® Infrared Modulation/Demodulation ® Two-wire EEPROMs and I ...
Page 3
... The AT91SAM7L128/64 are low power members of Atmel’s Smart ARM Microcontroller family based on the 32-bit ARM7 • AT91SAM7L128 features a 128 Kbyte high-speed Flash and a total of 6 Kbytes SRAM. • AT91SAM7L64 features a 64 Kbyte high-speed Flash and a total of 6 Kbytes SRAM. They also embed a large set of peripherals, including a Segment LCD Controller and a complete set of system functions minimizing the number of external components ...
Page 4
... Block Diagram Figure 2-1. AT91SAM7L128/64 Block Diagram TDI TDO TMS TCK JTAGSEL TST FIQ IRQ0-IRQ1 PCK0-PCK2 CLKIN PLL PLLRC XIN OSC XOUT 32k RCOSC VDDIO1 BOD POR VDDIO1 NRST NRSTB FWUP VDDIO1 DRXD DTXD SEG00-SEG39 COM0-COM9 RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 ...
Page 5
... TDI Test Data In TDO Test Data Out TMS Test Mode Select JTAGSEL JTAG Selection Flash and NVM Configuration Bits Erase ERASE Command 6257AS–ATARM–28-Feb-08 AT91SAM7L128/64 Preliminary Active Voltage Type Level Reference Comments Power Power Power Power Power Power Power ...
Page 6
... Timer Counter I/O Line B PWM0 - PWM3 PWM Channels MISO Master In Slave Out MOSI Master Out Slave In SPCK SPI Serial Clock NPCS0 SPI Peripheral Chip Select 0 NPCS1-NPCS3 SPI Peripheral Chip Select AT91SAM7L128/64 Preliminary 6 Active Voltage Type Level Reference Comments Reset/Test I/O Low VDDIO1 ...
Page 7
... Programming Ready PGMNVALID Data Direction PGMNOE Programming Read PGMCK Programming Clock PGMNCMD Programming Command COM[9:0] Common Terminals SEG[39:0] Segment Terminals 6257AS–ATARM–28-Feb-08 AT91SAM7L128/64 Preliminary Active Type Level Reference Comments Two-Wire Interface I/O I/O Analog-to-Digital Converter Input VDDCORE Input Analog VDDCORE ...
Page 8
... Package and Pinout The AT91SAM7L128/64 is available in: • 128-lead LQFP package with a 0.5 mm lead-pitch • 144-ball LFBGA package with a 0.8 mm pitch. The part is also available in die delivery. 4.1 128-lead LQFP Package Outline Figure 4-1 A detailed mechanical description is given in the Mechanical Characteristics section of the prod- uct datasheet ...
Page 9
... PA18 55 24 PA19 56 25 PA20 57 26 PA21 58 27 PA22 59 28 VDDCORE 60 29 PA23 61 30 PA24 62 31 PA25 63 32 VDDIO2 64 6257AS–ATARM–28-Feb-08 AT91SAM7L128/64 Preliminary VDDLCD 65 VDD3V6 66 CAPM2 67 CAPP2 68 CAPM1 69 CAPP1 70 VDDINLCD 71 GND 72 PB0 73 PB1 74 PB2 75 PB3 76 PB4 77 PB5 78 PB6 79 PB7 ...
Page 10
... LFBGA Package Outline Figure 4-2 A detailed mechanical description is given in the Mechanical Characteristics section of the prod- uct datasheet. Figure 4-2. AT91SAM7L128/64 Preliminary 10 shows the orientation of the 144-ball LFBGA package. 144-ball LFBGA Package Outline (Top View Ball A1 6257AS– ...
Page 11
... F5 C6 TDI F6 C7 PC22/PGMD11 F7 C8 PC19/PGMD8 F8 C9 PC16/PGMD5 F9 C10 PC9/PGMM2 F10 C11 PC10/PGMM3 F11 C12 PC8/PGMM1 F12 6257AS–ATARM–28-Feb-08 AT91SAM7L128/64 Preliminary Signal Name Pin Signal Name PA6 G1 VDD3V6 PA5 G2 PA17 PA7 G3 PA16 NC G4 PA15 PC26/PGMD15 G5 GND PC25/PGMD14 G6 GND PC21/PGMD11 ...
Page 12
... Power Supplies The AT91SAM7L128/64 has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are: • VDDOUT pin the output of the voltage regulator. Output voltage can be programmed from 1.55V to 1.80V by steps of 100 mV. • ...
Page 13
... When entering this mode, all PIO pins keep their previous states, they are reinitialized as inputs with pull-ups at wake-up. The AT91SAM7L128/64 can be awakened from this mode through the FWUP pin, an event on WUP0-15 pins RTC alarm or brownout event. Current consumption is 3.5 µA typical without the LCD controller running. ...
Page 14
... The fast restart circuitry, as shown in up signal to the power management controller. As soon as the fast start-up signal is asserted, the PMC automatically restarts the embedded 2 MHz Fast RC oscillator, switches the master clock on this 2 MHz clock and reenables the processor clock disabled. AT91SAM7L128/64 Preliminary 14 SLCK FWUPEN ...
Page 15
... Voltage Regulator The AT91SAM7L128/64 embeds a voltage regulator that is managed by the supply controller. This internal regulator is only intended to supply the internal core of AT91SAM7L128/64. It fea- tures three different operating modes: • In normal mode, the voltage regulator consumes less than 30 µA static current and draws output current. • ...
Page 16
... For example, two capacitors can be used in parallel, 100 nF NPO and 4.7 µF X7R. 5.6 LCD Power Supply The AT91SAM7L128/64 embeds an on-chip LCD power supply comprising a regulated charge pump and an adjustable voltage regulator. The regulated charge pump output delivers 3.6V as long as its input is supplied between 1.8V and 3 ...
Page 17
... If the charge pump is not needed, the user can apply an external voltage. See Figure 5-5. Please note that in this topology, switching time enhancement buffers are not available. (Refer Section 10.13 ”Segment LCD 6257AS–ATARM–28-Feb-08 AT91SAM7L128/64 Preliminary The LCD Regulator is Externally Supplied VDDIO2 VDDLCD ...
Page 18
... Typical Powering Schematics The AT91SAM7L128/64 supports a 1.8V-3.6V single supply mode. The internal regulator input connected to the source and its output feeds VDDCORE. ics to be used. Figure 5-6. AT91SAM7L128/64 Preliminary 18 3.3V System Single Power Supply Schematic VDDIO2 VDDLCD VDD3V6 VDDINLCD Main Supply (1.8V-3.6V) VDDIO1 VDDOUT ...
Page 19
... Test Pin The TST pin is used for manufacturing test or fast programming mode of the AT91SAM7L128/64 when asserted high. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. To enter fast programming mode, the TST and CLKIN pins must be tied high while FWUP is tied low ...
Page 20
... The PIO lines PC5 to PC8 are high-drive current capable. Each of these I/O lines can drive permanently. The remaining I/O lines can draw only 2 mA. Each I/O is designed to achieve very small leakage. However, the total current drawn by all the I/O lines cannot exceed 150 mA. AT91SAM7L128/64 Preliminary 20 6257AS–ATARM–28-Feb-08 ...
Page 21
... Remap Command – Remaps the SRAM in place of the embedded non-volatile memory – Allows handling of dynamic exception vectors – Peripheral protection against write and/or user access • Enhanced Embedded Flash Controller 6257AS–ATARM–28-Feb-08 AT91SAM7L128/64 Preliminary ® high-performance 32-bit instruction set 21 ...
Page 22
... Low bus arbitration overhead – One Master Clock cycle needed for a transfer from memory to peripheral – Two Master Clock cycles needed for a transfer from peripheral to memory • Next Pointer management for reducing interrupt latency requirements AT91SAM7L128/64 Preliminary 22 wait states 6257AS–ATARM–28-Feb-08 ...
Page 23
... Memories • 128 Kbytes of Flash Memory (AT91SAM7L128) – Single plane – One bank of 512 pages of 256 bytes – Fast access time, 15 MHz single-cycle access in Worst Case conditions – Page programming time: 4.6 ms, including page auto-erase – Page programming without auto-erase: 2.3 ms – Full chip erase time – ...
Page 24
... Undefined 14 x 256 MBytes (Abort) 3,584 MBytes 0xEFFF FFFF 0xF000 0000 Internal Peripherals 256M Bytes 0xFFFF FFFF AT91SAM7L128/64 Preliminary 24 Internal Memory Mapping 0x0000 0000 Boot Memory (1) 1 MBytes Flash before Remap SRAM after Remap 0x000F FFFF 0x0010 0000 Internal Flash ...
Page 25
... After remap, the 4-Kbyte Core SRAM also becomes available at address 0x0. The user can see the 6 Kbytes of SRAM contiguously at address 0x002F F000. 8.1.1.2 Internal ROM The AT91SAM7L128/64 embeds an Internal ROM. The ROM is always mapped at address 0x0040 0000. The ROM contains the FFPI and SAM-BA program. ROM size is 12 Kbytes. 8.1.1.3 Internal Flash • ...
Page 26
... Embedded Flash 8.1.2.1 Flash Overview • The Flash of the AT91SAM7L128 is organized in 512 pages (single plane) of 256 bytes. • The Flash of the AT91SAM7L64 is organized in 256 pages (single plane) of 256 bytes. The Flash contains a 128-byte write buffer, accessible through a 32-bit interface. 8.1.2.2 Flash Power Supply The Flash is supplied by VDDCORE through a power switch controlled by the Supply Controller ...
Page 27
... Flash organization, thus making the software generic. 8.1.2.4 Lock Regions The AT91SAM7L128 Embedded Flash Controller manages 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7L128 contains 16 lock regions and each lock region contains 32 pages of 256 bytes. Each lock region has a size of 8 Kbytes ...
Page 28
... The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when TST and CLKIN are tied high while FWUP is tied low. • The Flash of the AT91SAM7L128 is organized in 512 pages of 256 bytes (single plane). • The Flash of the AT91SAM7L64 is organized in 256 pages of 256 bytes (single plane). ...
Page 29
... The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF. ping of the System Controller. Note that the Memory Controller configuration user interface is also mapped within this address space 6257AS–ATARM–28-Feb-08 AT91SAM7L128/64 Preliminary Figure 9-1 on page Figure 8-1 on page 24 30. shows the map- ...
Page 30
... XIN Xtal 32 kHz Oscillator XOUT Embedded 32 kHz RC Oscillator Backup Power Supply core_nreset NRST FSTT0 - FSTT15 Embedded 2 MHz RC Oscillator FCIN SLCK PLLRC AT91SAM7L128/64 Preliminary 30 VDDIO1 vr_on vr_mode vr_ok supply_on Supply Controller lcd_mode lcd_out bod_on brown_out LCD Power Supply lcd_nreset rtc_on lcd_eof SLCK ...
Page 31
... Both monitor VDDIO1. The zero-power power-on reset circuit is always active. It provides an internal reset signal to the AT91SAM7L128/64 for power-on and power-off operations and ensures a proper reset for the Supply Controller. The brownout detection circuit is disabled by default and can be enabled by software. It monitors VDDIO1 ...
Page 32
... The unused oscillator is disabled so that power consumption is optimized. The 2 MHz Fast RC oscillator is the default selected clock (MAINCK) which is used at start-up . The user can select an external clock (CLKIN) through software. The PLL needs an external RC filter and starts very short time (inferior to 1 ms). AT91SAM7L128/64 Preliminary 32 6257AS–ATARM–28-Feb-08 ...
Page 33
... The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing reduced power consumption while waiting for an interrupt. The LCD Controller clock is SCLK. 6257AS–ATARM–28-Feb-08 AT91SAM7L128/64 Preliminary Clock Generator Block Diagram Clock Generator CLKIN Embedded ...
Page 34
... General Interrupt Mask – Provides processor synchronization on events without triggering an interrupt 9.7 Debug Unit • Comprises: – One two-pin UART – One Interface for the Debug Communication Channel (DCC) support AT91SAM7L128/64 Preliminary 34 Power Management Controller Block Diagram Master Clock Controller SLCK Prescaler MAINCK /1,/2,/4, ...
Page 35
... Offers visibility of COMMRX and COMMTX signals from the ARM Processor • Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of – Chip ID is 0x2733 0740 (VERSION 0) for AT91SAM7L128 – Chip ID is 0x2733 0540 (VERSION 0) for AT91SAM7L64 9.8 Period Interval Timer • ...
Page 36
... EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in 10.2 Peripheral Identifiers The AT91SAM7L128/64 embeds a wide range of peripherals. Identifiers of the AT91SAM7L128/64. Unique peripheral identifiers are defined for both the Advanced Interrupt Controller and the Power Management Controller. Table 10-1. Peripheral ID ...
Page 37
... Peripheral Multiplexing on PIO Lines The AT91SAM7L128/64 features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set. PIO Controller A, B and C control respectively 26, 24 and 30 lines. Each line can be assigned to one of two peripheral functions Table 10-2 on page 38 multiplexed on the PIO Controller A, B and C. The two columns “ ...
Page 38
... PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 AT91SAM7L128/64 Preliminary 38 Peripheral B Extra Function COM0 COM1 COM2 COM3 COM4 COM5 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 ...
Page 39
... PB16 RTS0 PB17 DTR1 PB18 PWM0 PB19 PWM1 PB20 PWM2 PB21 PWM3 PB22 NPCS1 PB23 PCK0 6257AS–ATARM–28-Feb-08 AT91SAM7L128/64 Preliminary PIO Controller B Peripheral B Extra Function SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 ...
Page 40
... PC25 TXD1 PC26 RTS0 PC27 NPCS2 PC28 SCK1 PC29 RTS1 Notes: 1. Wake-Up source in Backup mode (managed by the SUPC). 2. Fast Start-Up source in Wait mode (managed by the PMC). AT91SAM7L128/64 Preliminary 40 PIO Controller C Peripheral B Extra Functions PWM2 PGMEN0/WKUP0 TIOA2 PGMEN1/WKUP1 TIOB2 PGMEN2/WKUP2 TCLK1 PGMNCMD/WKUP3 ...
Page 41
... Optional break generation and detection – over-sampling receiver frequency – Hardware handshaking RTS - CTS – Modem Signals Management DTR-DSR-DCD-RI on USART1 – Receiver time-out and transmitter timeguard 6257AS–ATARM–28-Feb-08 AT91SAM7L128/64 Preliminary peripherals Sensors between clock and data ® and 3-wire EEPROMs ...
Page 42
... PWM Controller • Four channels, one 16-bit counter per channel • Common clock generator, providing thirteen different clocks – One Modulo n counter providing eleven clocks – Two independent linear dividers working on modulo n counter outputs AT91SAM7L128/64 Preliminary 42 Table 10-5 Timer Counter Clock Assignment Clock ...
Page 43
... Power-save mode display • Software-selectable low-power waveform capability • Flexible frame frequency selection • Segment and common pins, not needed for driving the display, can be used as ordinary I/O pins • Switching time enhancement internal buffers 6257AS–ATARM–28-Feb-08 AT91SAM7L128/64 Preliminary enabled channels 43 ...
Page 44
... Package Drawings Figure 11-1. 128-lead LQFP Package Drawing . Table 11-1. AT91SAM7L128/64 Table 11-2. JEDEC Drawing Reference JESD97 Classification Table 11-3. Moisture Sensitivity Level AT91SAM7L128/64 Preliminary 44 Device and LQFP Package Maximum Weight 800 Package Reference MS-026 e3 LQFP Package Characteristics 3 mg 6257AS–ATARM–28-Feb-08 ...
Page 45
... All dimensions are in mm Table 11-4. AT91SAM7L128/64 Table 11-5. JEDEC Drawing Reference JESD97 Classification Table 11-6. Moisture Sensitivity Level This package respects the recommendations of the NEMI User Group. 6257AS–ATARM–28-Feb-08 AT91SAM7L128/64 Preliminary Device and LFBGA Package Maximum Weight Package Reference MS-026 e1 LFBGA Package Characteristics ...
Page 46
... Ordering Information Table 12-1. Ordering Information Ordering Code AT91SAM7L128-AU AT91SAM7L64-AU AT91SAM7L128-CU AT91SAM7L64-CU AT91SAM7L128/64 Preliminary 46 Package Package Type LQFP128 Green LQFP128 Green LFBGA144 Green LFBGA144 Green Temperature Operating Range Industrial (-40°C to 85°C) Industrial (-40°C to 85°C) Industrial (-40°C to 85°C) Industrial (-40°C to 85°C) ...
Page 47
... Revision History Doc. Rev Comments 6257AS First issue 6257AS–ATARM–28-Feb-08 AT91SAM7L128/64 Preliminary Change Request Ref. 47 ...
Page 48
... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2008 Atmel Corporation. All rights reserved. Atmel marks or trademarks of Atmel Corporation or its subsidiaries. ARM marks of ARM Ltd. Other terms and product names may be trademarks of others. International ...