at91sam7l128 ATMEL Corporation, at91sam7l128 Datasheet - Page 21

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at91sam7l128

Manufacturer Part Number
at91sam7l128
Description
At91 Arm Thumb-based Microcontroller
Manufacturer
ATMEL Corporation
Datasheet

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7. Processor and Architecture
7.1
7.2
7.3
6257AS–ATARM–28-Feb-08
ARM7TDMI Processor
Debug and Test Features
Memory Controller
• RISC processor based on ARMv4T Von Neumann Architecture
• Two instruction sets
• Three-stage pipeline architecture
• Integrated embedded in-circuit emulator
• Debug Unit
• IEEE1149.1 JTAG Boundary-scan on all digital pins
• Programmable Bus Arbiter
• Address decoder provides selection signals for
• Abort Status Registers
• Misalignment Detector
• Remap Command
• Enhanced Embedded Flash Controller
– Runs at up to 36 MHz, providing 0.9 MIPS/MHz
– ARM
– Thumb high code density 16-bit instruction set
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Two watchpoint units
– Test access port accessible through a JTAG protocol
– Debug communication channel
– Two-pin UART
– Debug communication channel interrupt handling
– Chip ID Register
– Handles requests from the ARM7TDMI and the Peripheral DMA Controller
– Five internal 1 Mbyte memory areas
– One 256 Mbyte embedded peripheral area
– Source, Type and all parameters of the access leading to an abort are saved
– Facilitates debug by detection of bad pointers
– Alignment checking of all data accesses
– Abort generation in case of misalignment
– Remaps the SRAM in place of the embedded non-volatile memory
– Allows handling of dynamic exception vectors
– Peripheral protection against write and/or user access
®
high-performance 32-bit instruction set
AT91SAM7L128/64 Preliminary
21

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