at91sam9g45 ATMEL Corporation, at91sam9g45 Datasheet
at91sam9g45
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at91sam9g45 Summary of contents
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... Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os with Schmitt trigger input • Package – 324-ball TFBGA, pitch 0.8 mm AT91 ARM Thumb-based Microcontrollers AT91SAM9G45 Preliminary Summary NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. 6438CS–ATARM–13-Oct-09 ...
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... LCD Controller, resistive touch- screen, camera interface, audio, Ethernet 10/100 and high speed USB and SDIO. With the pro- cessor running at 400MHz and multiple 100+ Mbps data rate peripherals, the AT91SAM9G45 has the performance and bandwidth to the network or local storage media to provide an ade- quate user experience ...
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... Block Diagram Figure 2-1. AT91SAM9G45 Block Diagram 6438CS–ATARM–13-Oct-09 PIO AT91SAM9G45 3 ...
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... XOUT Main Oscillator Output XIN32 Slow Clock Oscillator Input XOUT32 Slow Clock Oscillator Output VBG Bias Voltage Reference for USB PCK0 - PCK1 Programmable Clock Output AT91SAM9G45 4 gives details on the signal names classified by peripheral. Active Type Level Power Supplies Power Power Power ...
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... Input Debug Unit - DBGU Input Output Advanced Interrupt Controller - AIC Input Input PIO Controller - PIOA- PIOB - PIOC - PIOD - PIOE I/O I/O AT91SAM9G45 Reference Voltage Comments Driven at 0V only. 0: The device is in backup mode VDDBU 1: The device is running (not in backup mode). Accept between 0V and VDDBU VDDBU ...
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... NWR0 - NWR3 Write Signal NRD Read Signal NWE Write Enable NBS0 - NBS3 Byte Mask Signal CFCE1 - CFCE2 CompactFlash Chip Enable CFOE CompactFlash Output Enable CFWE CompactFlash Write Enable CFIOR CompactFlash IO Read AT91SAM9G45 6 Active Reference Type Level (1) I/O (1) I/O (1) I/O I/O VDDIOM0 Output VDDIOM0 Output ...
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... Output Low Output Output Output High Speed Multimedia Card Interface - HSMCIx I/O I/O I/O I/O Output Input Output Input Synchronous Serial Controller - SSCx Output Input I/O I/O I/O I/O AT91SAM9G45 Reference Voltage Comments VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 (1) (1) ...
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... USB Host Port B High Speed Data - DFSDM USB Device Full Speed Data - DFSDP USB Device Full Speed Data + DHSDM USB Device High Speed Data - DHSDP USB Device High Speed Data + AT91SAM9G45 8 Active Type Level AC97 Controller - AC97C Input Output Output Input ...
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... LCD Controller - LCDC Output Output Output Output Output Output Output Output Touch Screen Analog-to-Digital Converter Analog Analog Analog AT91SAM9G45 Reference Voltage Comments (1) MII only, REFCK in RMII (1) MII only (1) (1) ETX0-ETX1 only in RMII (1) MII only (1) RXDV in MII, CRSDV in RMII ...
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... I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Inter- face signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column “Reset State” of the peripheral multiplexing tables. AT91SAM9G45 10 Active Reference ...
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... Package and Pinout The AT91SAM9G45 is delivered in a 324-ball TFBGA package. 4.1 Mechanical Overview of the 324-ball TFBGA Package Figure 4-1 Figure 4-1. 6438CS–ATARM–13-Oct-09 shows the orientation of the 324-ball TFBGA Package Orientation of the 324-ball TFBGA Package ...
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... TFBGA Package Pinout Table 4-1. AT91SAM9G45 Pinout for 324-ball BGA Package Pin Signal Name Pin A1 PC27 E10 A2 PC28 E11 A3 PC25 E12 A4 PC20 E13 A5 PC12 E14 A6 PC7 E15 A7 PC5 E16 A8 PC0 E17 A9 NWR3/NBS3 E18 A10 NCS0 F1 A11 DQS0 F2 A12 RAS F3 A13 SDCK ...
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... Table 4-1. AT91SAM9G45 Pinout for 324-ball BGA Package Pin Signal Name Pin C13 D10 H4 C14 D6 H5 C15 D2 H6 C16 GNDIOM H7 C17 A18 H8 C18 A12 H9 D1 XOUT32 H10 D2 PD20 H11 D3 GNDBU H12 D4 VDDBU H13 D5 PC24 H14 D6 PC18 H15 D7 PC13 H16 D8 PC6 H17 D9 NWR1/NBS1 ...
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... Power Considerations 5.1 Power Supplies The AT91SAM9G45 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 0.9V to 1.1V, 1.0V nominal. • VDDIOM0 pins: Power the DDR2/LPDDR I/O lines; voltage ranges between 1.65V and 1.95V (1.8V typical). • ...
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... Separate Address and Data Buses for both the 32-bit instruction interface and the – On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit • TCM Interface 6438CS–ATARM–13-Oct-09 each quarter of the page system flexibility 32-bit data interface (Words) AT91SAM9G45 15 ...
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... Allows Handling of Dynamic Exception Vectors 6.2.1 Matrix Masters The Bus Matrix of the AT91SAM9G45 manages Masters, thus each master can perform an access concurrently with others, depending on whether the slave it accesses is available. Each Master has its own decoder, which can be defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings ...
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... All the Masters can normally access all the Slaves. However, some paths do not make sense, such as allowing access from the Ethernet MAC to the internal peripherals. Thus, these paths are forbidden or simply not wired, and shown “-” in the following tables. Table 6-3. AT91SAM9G45 Masters to Slaves Access Master 0 ARM ...
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... SPI0 SSC1 SSC0 TSDAC DBGU USART3 USART2 USART1 USART0 AC97 SPI1 SPI0 SSC1 SSC0 AT91SAM9G45 18 summarizes the Slave Memory Mapping for each connected Master, depending on Internal Memory Mapping RCBx = 0 Slave BMS = 1 Internal ROM Peripheral DMA Controller Channel T/R Transmit Transmit Transmit Transmit ...
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... USB The AT91SAM9G45 features USB communication ports as follows: • 2 Ports USB Host full speed OHCI and High speed EHCI • 1 Device High speed USB Host Port A is directly connected to the first UTMI transceiver. The Host Port B is multiplexed with the USB device High speed and connected to the second UTMI port ...
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... Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins. AT91SAM9G45 20 DMA Channel Definition DMA Channel HW T/R interface Number RX ...
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... Memories Figure 7-1. AT91SAM9G45 Memory Mapping Address Memory Space 0x00000000 Internal Memories 0x10000000 EBI Chip Select 0 0x20000000 EBI Chip Select 1 DDR2-LPDDR-SDRAM 0x30000000 EBI Chip Select 2 0x40000000 EBI Chip Select 3 NANDFlash 0x50000000 EBI Chip Select 4 Compact Flash Slot 0 0x60000000 EBI Chip Select 5 Compact Flash Slot 1 ...
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... Embedded Memories 7.2.1 Internal SRAM The AT91SAM9G45 product embeds a total of 64 Kbytes high-speed SRAM split in 4 blocks of 16 KBytes connected to one slave of the matrix. After reset and until the Remap Command is performed, the four SRAM blocks are contiguous and only accessible at address 0x00300000. ...
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... Note: All the memory blocks can always be seen at their specified base addresses that are not concerned by these parameters. The AT91SAM9G45 Bus Matrix manages a boot memory that depends on the level on the pin BMS at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect. 6438CS– ...
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... Reprogram the SMC setup, cycle, hold, mode timings registers for EBI CS0 to adapt them to the new clock • Switch the main clock to the new value 7.3 External Memories The AT91SAM9G45 features an External Bus Interface to interface to a wide range of external memories and to any parallel peripheral. 7.3.1 DDR2/LPDDR Interface • Integrates 4-ports DDR2/LPDDR controller that support: – ...
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... Self-refresh, Power-down and Deep Power Modes Supported • Power-up Initialization by Software • CAS Latency Supported • Reset function supported (DDR2) • Auto Precharge Command Not Used • On Die Termination not supported • OCD mode not supported 6438CS–ATARM–13-Oct-09 Average Latency of Transactions) AT91SAM9G45 TM M support 25 ...
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... Tracking the accesses to a NAND Flash device by triggering on the corresponding chip select • Single bit error correction and 2-bit Random detection. • Automatic Hamming Code Calculation while writing – ECC value available in a register • Automatic Hamming Code Calculation while reading AT91SAM9G45 26 Average Latency of Transactions) 6438CS–ATARM–13-Oct-09 ...
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... Error Report, including error flag, correctable error flag and word address being – Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes 6438CS–ATARM–13-Oct-09 detected erroneous pages AT91SAM9G45 27 ...
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... All the registers of the System Controller can be addressed from a single pointer by using the standard ARM instruction set, as the Load/Store instruction have an indexing mode of ±4 KB. Figure 8-1 on page 29 Figure 7-1 on page 21 peripherals. AT91SAM9G45 28 shows the System Controller block diagram. shows the mapping of the User Interfaces of the System Controller 6438CS–ATARM–13-Oct-09 ...
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... System Controller Block Diagram Figure 8-1. AT91SAM9G45 System Controller Block Diagram periph_irq[2..24] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset backup_nreset SHDN WKUP RC OSC SLOW XIN32 CLOCK XOUT32 OSC XIN 12MHz MAIN OSC XOUT ...
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... MHz input, the only limitation being the lowest input frequency shall be higher or equal to 2 MHz. The USB Device and Host HS Clocks are provided by a the dedicated UTMI PLL (UPLL) embedded in the UTMI macro. AT91SAM9G45 30 6438CS–ATARM–13-Oct-09 ...
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... Figure 8-2. 8.6 Slow Clock Selection The AT91SAM9G45 slow clock can be generated either by an external 32768Hz crystal or the on-chip RC oscillator. The 32768 Hz crystal oscillator can be bypassed, by setting the bit OSC32BYP, to accept an external slow clock on XIN32. The internal RC oscillator and the 32768 Hz oscillator can be enabled by setting to 1 respec- tively RCEN bit and OSC32EN bit in the system controller user interface ...
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... Switch the master clock to a source different from slow clock (PLLA or PLLB or Main Oscillator). • Enable the internal RC oscillator by setting the bit RCEN to 1. • Wait internal RC Startup Time for clock stabilization (software loop). AT91SAM9G45 32 Slow Clock Clock Generator On Chip ...
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... Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt • Backup Mode, Main Power Supplies off, VDDBU powered by a battery 6438CS–ATARM–13-Oct-09 DDR system clock is not available when Master Clock (MCK) equals Processor Clock (PCK). AT91SAM9G45 33 ...
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... Full Speed OHCI input clock is UPLLCK, USBDIV is 9 (division by 10) • System Input clock is UPLLCK, Prescaler is 2, PCK is 240 MHz • MDIV is ‘01’, MCK is 120 MHz • Only LP-DDR can be used 120 MHz AT91SAM9G45 34 AT91SAM9G45 Power Management Controller Block Diagram USBS USBDIV+1 UPLLCK X /1 /1.5 /2 Prescaler /1 /2 /1,/2,/4, ...
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... Thirty-two individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.) – Programmable Edge-triggered or Level-sensitive Internal Sources – Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive 6438CS–ATARM–13-Oct-09 Controller AT91SAM9G45 35 ...
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... Debug Communication Channel Support – Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from 8.15 Chip Identification The AT91SAM9G45 Chip ID is defined in the Debug Unit Chip ID Register and Debug Unit Chip ID Extension Register. • Chip ID: 0x819B05A2 • Ext ID: 0x00000004 • ...
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... Multi-drive option enables driving in open drain – Programmable pull up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write 6438CS–ATARM–13-Oct-09 AT91SAM9G45 37 ...
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... Reserved 31 AIC AT91SAM9G45 38 Figure 7-1, the Peripherals are mapped in the upper 256 Mbytes of the address defines the Peripheral Identifiers of the AT91SAM9G45. A peripheral identifier is Peripheral Name Advanced Interrupt Controller System Controller Interrupt Parallel I/O Controller A, Parallel I/O Controller B Parallel I/O Controller C Parallel I/O Controller D/E True Random Number Generator ...
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... Peripheral ID. However, there is no clock control associated with these peripheral IDs. 9.4 Peripheral Signals Multiplexing on I/O Lines The AT91SAM9G45 features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which mul- tiplexes the I/O lines of the peripheral set. Each PIO Controller controls lines. Each line can be assigned to one of two peripheral functions The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two columns “ ...
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... PA20 TWD0 PA21 TWCK0 PA22 MCI1_CDA PA23 MCI1_DA0 PA24 MCI1_DA1 PA25 MCI1_DA2 PA26 MCI1_DA3 PA27 MCI1_DA4 PA28 MCI1_DA5 PA29 MCI1_DA6 PA30 MCI1_DA7 PA31 MCI1_CK AT91SAM9G45 40 Reset Power Peripheral B State Supply TCLK3 I/O VDDIOP0 TIOA3 I/O VDDIOP0 TIOB3 I/O VDDIOP0 TCKL4 I/O VDDIOP0 TIOA4 I/O VDDIOP0 TIOB4 I/O ...
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... VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 ISI_D8 I/O VDDIOP2 ISI_D9 I/O VDDIOP2 ISI_D10 I/O VDDIOP2 ISI_D11 I/O VDDIOP2 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 CTS0 I/O VDDIOP0 SCK0 I/O VDDIOP0 RTS0 I/O VDDIOP0 SPI0_NPCS1 I/O VDDIOP0 SPI0_NPCS2 I/O VDDIOP0 I/O VDDIOP2 I/O VDDIOP2 I/O VDDIOP2 I/O VDDIOP2 I/O VDDIOP2 I/O VDDIOP2 I/O VDDIOP2 I/O VDDIOP2 I/O VDDIOP2 I/O VDDIOP2 I/O VDDIOP2 PCK1 I/O VDDIOP2 AT91SAM9G45 Function Comments 41 ...
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... D21 PC22 D22 PC23 D23 PC24 D24 PC25 D25 PC26 D26 PC27 D27 PC28 D28 PC29 D29 PC30 D30 PC31 D31 AT91SAM9G45 42 Reset Power Peripheral B State Supply DQM2 VDDIOM1 DQM3 VDDIOM1 A19 VDDIOM1 A20 VDDIOM1 A21 VDDIOM1 A22 VDDIOM1 A23 VDDIOM1 ...
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... VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 IRQ I/O VDDIOP0 FIQ I/O VDDIOP0 I/O VDDANA I/O VDDANA I/O VDDANA I/O VDDANA PWM0 I/O VDDANA PWM1 I/O VDDANA PWM2 I/O VDDANA SPI0_NPCS3 I/O VDDANA SPI1_NPCS1 I/O VDDIOP0 SCK1 I/O VDDIOP0 SCK2 I/O VDDIOP0 PWM1 I/O VDDIOP0 AT91SAM9G45 Function Comments TSAD0 TSAD1 TSAD2 TSAD3 GPAD4 GPAD5 GPAD6 GPAD7 43 ...
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... LCDD12 PE20 LCDD13 PE21 LCDD14 PE22 LCDD15 PE23 LCDD16 PE24 LCDD17 PE25 LCDD18 PE26 LCDD19 PE27 LCDD20 PE28 LCDD21 PE29 LCDD22 PE30 LCDD23 PE31 PWM2 AT91SAM9G45 44 Reset Power Peripheral B State Supply PCK0 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 LCDD2 I/O VDDIOP1 ...
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... Asynchronous Mode stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB- or LSB-first 6438CS–ATARM–13-Oct-09 peripherals Sensors and data per chip select AT91SAM9G45 45 ...
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... Variable sampling rate AC97 Codec Interface (48KHz and below) 10.6 Timer Counter (TC) • Three 16-bit Timer Counter Channels • Wide range of functions including: – Frequency Measurement – Event Counting – Interval Measurement – Pulse Generation AT91SAM9G45 TDM Buses, Magnetic Card Reader,...) 6438CS–ATARM–13-Oct-09 ...
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... Root Hub Integrated with 2 Downstream USB Ports • Shared 10.10 USB High Speed Device Port (UDPHS) • USB V2.0 high-speed compliant, 480 MBits per second • Embedded USB V2.0 UTMI+ high-speed transceiver shared with UHP HS. 6438CS–ATARM–13-Oct-09 Embedded USB Transceivers AT91SAM9G45 47 ...
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... Automatic wakeup on trigger and back to sleep mode after conversions of all 10.13 Ethernet 10/100 MAC (EMAC) • Compatibility with IEEE Standard 802.3 • 10 and 100 MBits per second data throughput capability • Full- and half-duplex operations AT91SAM9G45 48 enabled channels 6438CS–ATARM–13-Oct-09 ...
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... Auto-loading of source, destination and control registers from system memory at end – Unaligned system address to data transfer width supported in hardware • Channel Buffering 6438CS–ATARM–13-Oct-09 lists transfer. Writing a stream of data into non-contiguous fields in system memory transfer programmed values at the end of a block transfer of block transfer in block chaining mode AT91SAM9G45 49 ...
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... Support for Software handshaking interface. Memory mapped registers can be used to control the flow of a DMA transfer in place of a hardware handshaking interface • Interrupt – Programmable Interrupt generation on DMA Transfer completion Block Transfer completion, Single/Multiple transaction completion or Error condition AT91SAM9G45 50 6438CS–ATARM–13-Oct-09 ...
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... Mechanical Characteristics 11.1 Package Drawings Figure 11-1. 324-ball TFBGA Package Drawing 6438CS–ATARM–13-Oct-09 AT91SAM9G45 51 ...
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... AT91SAM9G45 Ordering Information Table 12-1. AT91SAM9G45 Ordering Information Ordering Code AT91SAM9G45-CU AT91SAM9G45 52 Package Package Type TFBGA324 Green Temperature Operating Range Industrial -40°C to 85°C 6438CS–ATARM–13-Oct-09 ...
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... Table 4-1, updated. “Features” part and Section 4.1 “Mechanical Overview of the 324-ball Table 3-1, Touch Screen Analog-to-Digital Converter9 Ground pins GND are common to...” sentence in Section 7.2.3 “Internal AT91SAM9G45 part was edited. Section 5.1 “Power ROM”. Change Request Ref. 6600 6669 6715 RFO ...
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