at91sam9g45 ATMEL Corporation, at91sam9g45 Datasheet - Page 16

• Manufacturer Part Number: at91sam9g45
• Description: At91 Arm Thumb-based Microcontrollers
• Manufacturer: ATMEL Corporation

6.2
6.2.1
16
Bus Matrix
AT91SAM9G45
Matrix Masters
The Bus Matrix of the AT91SAM9G45 manages Masters, thus each master can perform an
access concurrently with others, depending on whether the slave it accesses is available.
Each Master has its own decoder, which can be defined specifically for each master. In order to
simplify the addressing, all the masters have the same decodings.
Table 6-1.
Master 0
Master 1
Master 2
Master 3
Master 4
Master 5
Master 6
Master 7
Master 8
Master 9
Master 10
• 11-layer Matrix, handling requests from 11 masters
• Programmable Arbitration strategy
• Burst Management
• One Address Decoder provided per Master
• Boot Mode Select
• Remap Command
– Fixed-priority Arbitration
– Round-Robin Arbitration, either with no default master, last accessed default master
– Breaking with Slot Cycle Limit Support
– Undefined Burst Length Support
– Three different slaves may be assigned to each decoded memory area: one for
– Non-volatile Boot Memory can be internal ROM or external memory on EBI_NCS0
– Selection is made by General purpose NVM bit sampled at reset
– Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
– Allows Handling of Dynamic Exception Vectors
or fixed default master
internal ROM boot, one for internal flash boot, one after remap
(ROM or External Flash)
List of Bus Matrix Masters
ARM926
ARM926 Data
Peripheral DMA Controller (PDC)
LCD DMA
Ethernet MAC DMA
USB Device High Speed DMA
USB Host High Speed EHCI DMA
USB HOST OHCI
DMA
DMA
ISI Controller DMA
™
Instruction
6438CS–ATARM–13-Oct-09