at91sam9g45 ATMEL Corporation, at91sam9g45 Datasheet - Page 26

• Manufacturer Part Number: at91sam9g45
• Description: At91 Arm Thumb-based Microcontrollers
• Manufacturer: ATMEL Corporation

7.3.4
7.3.5
7.3.6
26
AT91SAM9G45
Static Memory Controller
DDR2/SDR Controller
NAND Flash Error Corrected Code Controller
• 8-, 16- or 32-bit Data Bus
• Multiple Access Modes supported
• Multiple device adaptability
• Multiple Wait State Management
• Slow Clock mode supported
• Supports DDR2/LPDDR2, SDR-SDRAM and LPSDR
• Numerous Configurations Supported
• Programming Facilities
• Energy-saving Capabilities
• SDRAM Power-up Initialization by Software
• CAS Latency of 2, 3 Supported
• Auto Precharge Command Not Used
• SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported
• Tracking the accesses to a NAND Flash device by triggering on the corresponding chip select
• Single bit error correction and 2-bit Random detection.
• Automatic Hamming Code Calculation while writing
• Automatic Hamming Code Calculation while reading
– Byte Write or Byte Select Lines
– Asynchronous read in Page Mode supported (4- up to 32-byte page size)
– Control signals programmable setup, pulse and hold time for each Memory Bank
– Programmable Wait State Generation
– External Wait Request
– Programmable Data Float Time
– 2K, 4K, 8K, 16K Row Address Memory Parts
– SDRAM with Four Internal Banks
– SDR-SDRAM with 16- or 32- bit Data Path
– DDR2/LPDDR with 16- bit Data Path
– One Chip Select for SDRAM Device (256 Mbyte Address Space)
– Multibank Ping-pong Access (Up to 4 Banks Opened at Same Time = Reduces
– Timing Parameters Specified by Software
– Automatic Refresh Operation, Refresh Rate is Programmable
– Automatic Update of DS, TCR and PASR Parameters (LPSDR)
– Self-refresh, Power-down and Deep Power Modes Supported
– Clock Frequency Change in Precharge Power-down Mode Not Supported
– ECC value available in a register
Average Latency of Transactions)
6438CS–ATARM–13-Oct-09