at91sam9g25-cu ATMEL Corporation, at91sam9g25-cu Datasheet

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at91sam9g25-cu

Manufacturer Part Number
at91sam9g25-cu
Description
At91sam Arm-based Embedded Mpu
Manufacturer
ATMEL Corporation
Datasheet

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Features
Core
Memories
System running at up to 133 MHz
Low Power Mode
Peripherals
I/O
Packages
– ARM926EJ-S™ ARM
– 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit
– One 64-Kbyte internal ROM embedding bootstrap routine: Boot on NAND Flash,
– One 32-Kbyte internal SRAM, single-cycle access at system speed
– High Bandwidth Multi-port DDR2 Controller
– 32-bit External Bus Interface supporting 8-bank DDR2/LPDDR, SDR/LPSDR, Static
– MLC/SLC NAND Controller, with up to 24-bit Programmable Multi-bit Error
– Power-on Reset Cells, Reset Controller, Shut Down Controller, Periodic Interval
– Boot Mode Select Option, Remap Command
– Internal Low Power 32 kHz RC and Fast 12 MHz RC Oscillators
– Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator
– One PLL for the system and one PLL at 480 MHz optimized for USB High Speed
– Twelve 32-bit-layer AHB Bus Matrix for large Bandwidth transfers
– Dual Peripheral Bridge with dedicated programmable clock for best performance
– Two dual port 8-channel DMA Controllers
– Advanced Interrupt Controller and Debug Unit
– Two Programmable External Clock Signals
– Shut Down Controller with four 32-bit Battery Backup Registers
– Clock Generator and Power Management Controller
– Very Slow Clock Operating Mode, Software Programmable Power Optimization
– ITU-R BT. 601/656 Image Sensor Interface
– USB Device High Speed, USB Host High Speed and USB Host Full Speed with
– One 10/100 Mbps Ethernet MAC Controller
– Two High Speed Memory Card Hosts
– Two Master/Slave Serial Peripheral Interface
– Two Three-channel 32-bit Timer/Counters
– One Synchronous Serial Controller
– One Four-channel 16-bit PWM Controller
– Three Two-wire Interfaces
– Four USARTs, two UARTs
– One 12-channel 10-bit Analog-to-Digital Converter
– Soft Modem
– Four 32-bit Parallel Input/Output Controllers
– 105 Programmable I/O Lines Multiplexed with up to Three Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line, optional Schmitt trigger input
– Individually Programmable Open-drain, Pull-up and pull-down resistor,
– 217-ball BGA, pitch 0.8 mm
– 247-ball BGA, pitch 0.5 mm
SDCard, DataFlash
Memories
Correcting Code (PMECC)
Timer, Watchdog Timer and Real Time Clock
Capabilities
dedicated On-Chip Transceiver
Synchronous Output
®
®
or serial DataFlash. Programmable order.
Thumb
®
Processor running at up to 400 MHz @ 1.0V +/- 10%
AT91SAM
ARM-based
Embedded MPU
SAM9G25
Summary
NOTE: This is a summary document.
The complete document is available on
the Atmel website at www.atmel.com.
11032AS–ATARM–27-Jul-11

Related parts for at91sam9g25-cu

at91sam9g25-cu Summary of contents

Page 1

Features • Core ® – ARM926EJ-S™ ARM Thumb – 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit • Memories – One 64-Kbyte internal ROM embedding bootstrap routine: Boot on NAND Flash, ® SDCard, DataFlash or serial DataFlash. ...

Page 2

Description Based on the ARM926EJ-S core, the SAM9G25 is an embedded microprocessor unit, running at 400 MHz and featuring connectivity peripherals, a high data bandwidth architecture and a small footprint package option, making it an optimized solution for industrial ...

Page 3

Block Diagram Figure 2-1. SAM9G25 Block Diagram 11032AS–ATARM–27-Jul-11 PIO PIO SAM9G25 3 ...

Page 4

Signal Description Table 3-1 Table 3-1. Signal Description List Signal Name Function XIN Main Oscillator Input XOUT Main Oscillator Output XIN32 Slow Clock Oscillator Input XOUT32 Slow Clock Oscillator Output VBG Bias Voltage Reference for USB PCK0-PCK1 Programmable Clock ...

Page 5

Table 3-1. Signal Description List (Continued) Signal Name Function D0-D15 Data Bus D16-D31 Data Bus A0-A25 Address Bus NWAIT External Wait Signal NCS0-NCS5 Chip Select Lines NWR0-NWR3 Write Signal NRD Read Signal NWE Write Enable NBS0-NBS3 Byte Mask Signal NFD0-NFD16 ...

Page 6

Table 3-1. Signal Description List (Continued) Signal Name Function Universal Synchronous Asynchronous Receiver Transmitter - USARTx SCKx USARTx Serial Clock TXDx USARTx Transmit Data RXDx USARTx Receive Data RTSx USARTx Request To Send CTSx USARTx Clear To Send UTXDx UARTx ...

Page 7

Table 3-1. Signal Description List (Continued) Signal Name Function PWM0-PWM3 Pulse Width Modulation Output HFSDPA USB Host Port A Full Speed Data + HFSDMA USB Host Port A Full Speed Data - HHSDPA USB Host Port A High Speed Data ...

Page 8

Table 3-1. Signal Description List (Continued) Signal Name Function DIBN Soft Modem Signal DIBP Soft Modem Signal SAM9G25 8 Soft Modem - SMD Type Active Level I/O I/O 11032AS–ATARM–27-Jul-11 ...

Page 9

Package and Pinout The SAM9G25 is available in 217-ball BGA and 247-ball BGA packages. 4.1 Overview of the 217-ball BGA Package Figure 4-1 Figure 4-1. 4.2 Overview of the 247-ball BGA Package Figure 4-2 Figure 4-2. 11032AS–ATARM–27-Jul-11 shows the ...

Page 10

I/O Description Table 4-1. I/O Type GPIO GPIO_CLK GPIO_CLK2 GPIO_ANA EBI EBI_O EBI_CLK RSTJTAG SYSC VBG USBFS USBHS CLOCK DIB When “Reset State” is mentioned, the configuration is defined by the “Reset State” column of the Pin Description table. ...

Page 11

Table 4-2. I/O Type USBFS USBHS CLOCK DIB 4.3.1 Reset State In the tables that follow, the column “Reset State” indicates the reset state of the line with mnemonics. • “PIO” “/” signal Indicates whether the PIO Line resets in ...

Page 12

BGA Package Pinout Table 4-3. Pin Description BGA217 Ball Power Rail I/O Type Signal L3 VDDIOP0 GPIO PA0 P1 VDDIOP0 GPIO PA1 L4 VDDIOP0 GPIO PA2 N4 VDDIOP0 GPIO PA3 T3 VDDIOP0 GPIO PA4 R1 VDDIOP0 GPIO PA5 ...

Page 13

Table 4-3. Pin Description BGA217 (Continued) Ball Power Rail I/O Type Signal C5 VDDANA GPIO_ANA PB8 C1 VDDANA GPIO_ANA PB9 B2 VDDANA GPIO_ANA PB10 A3 VDDANA GPIO_ANA PB11 B4 VDDANA GPIO_ANA PB12 A2 VDDANA GPIO_ANA PB13 C4 VDDANA GPIO_ANA PB14 ...

Page 14

Table 4-3. Pin Description BGA217 (Continued) Ball Power Rail I/O Type Signal P13 VDDNF EBI PD0 R14 VDDNF EBI PD1 R13 VDDNF EBI PD2 P15 VDDNF EBI PD3 P12 VDDNF EBI PD4 P14 VDDNF EBI PD5 N14 VDDNF EBI PD6 ...

Page 15

Table 4-3. Pin Description BGA217 (Continued) Ball Power Rail I/O Type Signal U16 VDDUTMII POWER VDDUTMII T17 VDDUTMIC POWER VDDUTMIC T16 GNDUTMI GND GNDUTMI D14 VDDIOM EBI D15 VDDIOM EBI A16 VDDIOM EBI B16 VDDIOM EBI A17 VDDIOM EBI B15 ...

Page 16

Table 4-3. Pin Description BGA217 (Continued) Ball Power Rail I/O Type Signal C7 VDDIOM EBI_O NWR1 A8 VDDIOM EBI_O NWR3 D11 VDDIOM EBI_CLK SDCK C11 VDDIOM EBI_CLK #SDCK B12 VDDIOM EBI_O SDCKE B11 VDDIOM EBI_O RAS C10 VDDIOM EBI_O CAS ...

Page 17

BGA Package Pinout Table 4-4. Pin Description BGA247 Ball Power Rail I/O Type Signal P2 VDDIOP0 GPIO P3 VDDIOP0 GPIO M7 VDDIOP0 GPIO T2 VDDIOP0 GPIO N5 VDDIOP0 GPIO V1 VDDIOP0 GPIO U2 VDDIOP0 GPIO W1 VDDIOP0 GPIO ...

Page 18

Table 4-4. Pin Description BGA247 (Continued) Ball Power Rail I/O Type Signal B2 VDDANA GPIO_ANA PB8 C2 VDDANA GPIO_ANA PB9 B1 VDDANA GPIO_ANA PB10 B5 VDDANA GPIO_ANA PB11 E5 VDDANA GPIO_ANA PB12 B4 VDDANA GPIO_ANA PB13 A1 VDDANA GPIO_ANA PB14 ...

Page 19

Table 4-4. Pin Description BGA247 (Continued) Ball Power Rail I/O Type Signal N2 VDDIOP1 GPIO P11 VDDNF EBI U15 VDDNF EBI VDDCORE P14 VDDNF EBI R15 VDDNF EBI R14 VDDNF EBI P12 VDDNF EBI N15 VDDNF EBI P15 VDDNF EBI ...

Page 20

Table 4-4. Pin Description BGA247 (Continued) Ball Power Rail I/O Type Signal M14 GNDIOM GND GNDIOM N14 GNDIOM GND GNDIOM P18 GNDIOM GND GNDIOM N8 VDDIOP0 POWER VDDIOP0 R10 VDDIOP0 POWER VDDIOP0 J5 VDDIOP1 POWER VDDIOP1 J9 GNDIOP GND GNDIOP ...

Page 21

Table 4-4. Pin Description BGA247 (Continued) Ball Power Rail I/O Type Signal E14 VDDIOM EBI A16 VDDIOM EBI B15 VDDIOM EBI A14 VDDIOM EBI E13 VDDIOM EBI C14 VDDIOM EBI F12 VDDIOM EBI D13 VDDIOM EBI B13 VDDIOM EBI A12 ...

Page 22

Table 4-4. Pin Description BGA247 (Continued) Ball Power Rail I/O Type Signal G10 VDDIOM EBI_O RAS C11 VDDIOM EBI_O CAS H10 VDDIOM EBI_O SDWE G9 VDDIOM EBI_O SDA10 B11 VDDIOM EBI_O DQM0 J10 VDDIOM EBI_O DQS0 E10 VDDIOM EBI DQM1 ...

Page 23

Power Considerations 5.1 Power Supplies The SAM9G25 has several types of power supply pins. Table 5-1. SAM9G25 Power Supplies Name Voltage Range, nominal VDDCORE 0.9-1.1V, 1.0V 1.65-1.95V, 1.8V VDDIOM 3.0-3.6V, 3.3V 1.65-1.95V, 1.8V VDDNF 3.0-3.6V, 3.3V VDDIOP0 1.65-3.6V VDDIOP1 ...

Page 24

Processor and Architecture 6.1 ARM926EJ-S Processor • RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration • Two Instruction Sets – ARM High-performance 32-bit Instruction Set – Thumb High Code Density 16-bit Instruction Set • ...

Page 25

... APB/AHB Bridge The AT91SAM9G25 product embeds two separated APB/AHB bridges. This architecture enables to make concurrent access on both bridges. Each peripheral can be clocked at a lower speed (MCK divided clock) in order to decrease the current consumption. 6.3 Bus Matrix • 12-layer Matrix, handling requests from 11 masters • ...

Page 26

... Master 1 Master 2&3 Master 4&5 Master 6 Master 7 Master 8 Master 9 Master 10 6.5 Matrix Slaves The Bus Matrix of the AT91SAM9G25 product manages 9 slaves. Each slave has its own arbi- ter, allowing a different arbitration per slave. Table 6-2. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 Slave 6 Slave 7 ...

Page 27

... All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the USB Device High speed DMA to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown as “-” in the following table. Table 1. AT91SAM9G25 Master to Slave Access Masters 0 ...

Page 28

... USB The AT91SAM9G25 features the following USB communication ports: • 2 Hosts (A and B) High Speed (EHCI) and Full Speed (OHCI) • 1 Host (C) Full Speed only (OHCI) • 1 Device High Speed The High Speed USB Host Port A is shared with the High Speed USB Device port and con- nected to the second UTMI transceiver ...

Page 29

DMA Controller 0 • Two Masters • Embeds 8 channels • 64-byte FIFO for channel 0, 16-byte FIFO for Channel • features: – Linked List support with Status Write Back operation at End of Transfer – ...

Page 30

DMA Controller 1 • Two Masters • Embeds 8 channels • 16-byte FIFO per Channel • features: – Linked List support with Status Write Back operation at End of Transfer – Word, HalfWord, Byte transfer support. – Peripheral to ...

Page 31

Debug and Test Features • ARM926 Real-time In-circuit Emulator – Two real-time Watchpoint Units – Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug ...

Page 32

Memories Figure 7-1. SAM9G25 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256 MBytes 0x0FFF FFFF 0x1000 0000 EBI 256 MBytes Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1 256 MBytes DDR2/LPDDR SDR/LPSDR 0x2FFF FFFF ...

Page 33

Memory Mapping A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 ...

Page 34

Multiple device adaptability – Control signals programmable setup, pulse and hold time for each Memory Bank • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time • Slow Clock mode ...

Page 35

System Controller The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure ...

Page 36

Figure 8-1. SAM9G25 System Controller Block Diagram periph_irq[2..30] pit_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset SHDN WKUP XIN32 SLOW CLOCK XOUT32 OSC 12M RC XIN 12MHz MAIN OSC XOUT UPLL PLLA periph_nreset ...

Page 37

Chip Identification • Chip ID: 0x819A_05A1 • Chip ID Extension: 3 • JTAG ID: 0x05B2_F03F • ARM926 TAP ID: 0x0792_603F 8.2 Backup Section The SAM9G25 features a Backup Section that embeds: • RC Oscillator • Slow Clock Oscillator • ...

Page 38

Peripherals 9.1 Peripheral Mapping As shown in space between the addresses 0xF000 0000 and 0xFFFF C000. Each User Peripheral is allocated 16 Kbytes of address space. 9.2 Peripheral Identifiers Table 9-1 for the control of the peripheral interrupt with ...

Page 39

Table 9-1. Instance 9.3 Peripheral Signal Multiplexing on I/O Lines The SAM9G25 features 4 PIO Controllers, PIOA, PIOB, PIOC and PIOD, which multiplex the I/O lines of the peripheral set. Each PIO ...

Page 40

Embedded Peripherals Overview 10.1 Serial Peripheral Interface (SPI) • Two SPIs • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with – Serial memories, such as DataFlash and ...

Page 41

MSB- or LSB-first – Optional break generation and detection – by-16 over-sampling receiver frequency – Hardware handshaking RTS-CTS – Receiver time-out and transmitter timeguard – Optional Multi-drop Mode with address generation and detection – Optional Manchester ...

Page 42

Serial Synchronous Controller (SSC) • One SSC • Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I • Contains an independent receiver and transmitter and a common clock divider ...

Page 43

High Speed USB Host Port (UHPHS) • Compliant with EnhancedHCI Rev 1.0 Specification – Compliant with USB V2.0 High-speed and Full-speed Specification – Supports Both High-speed 480Mbps and Full-speed 12 Mbps USB devices • Compliant with OpenHCI Rev 1.0 ...

Page 44

Ethernet 10/100 MAC (EMAC) • supports MII Mode • Compatibility with IEEE Standard 802.3 • 10 and 100 Mbits per second data throughput capability • Full- and half-duplex operations • Register Interface to address, data, status and control registers ...

Page 45

DMA chaining support for multiple non-contiguous data blocks through use of linked – Scatter support for placing fields into a system memory area from a contiguous – Gather support for extracting fields from a system memory area into a ...

Page 46

Soft Modem (SMD) • Modulations and protocols – V.90 – V.34 – V.32bis, V.32, V.22bis, V.22, V.23, V.21 – V.23 reverse, V.23 half-duplex – Bell 212A/Bell 103 – V.29 FastPOS – V.22bis fast connect – V.80 Synchronous Access Mode ...

Page 47

Mechanical Overview Figure 11-1. 217-ball BGA Package Drawing 11032AS–ATARM–27-Jul-11 SAM9G25 47 ...

Page 48

Table 11-1. 217-ball BGA Package Characteristics Moisture Sensitivity Level Table 11-2. Package Reference JEDEC Drawing Reference JESD97 Classification Table 11-3. Soldering Information Ball Land Solder Mask Opening SAM9G25 48 3 MO-205 e1 0.43 mm ± 0.05 0.30 mm ± 0.05 ...

Page 49

Figure 11-2. 247-ball BGA Package Drawing 11032AS–ATARM–27-Jul-11 SAM9G25 49 ...

Page 50

Table 11-4. Ball Information Ball Pitch Ball Diameter Table 11-5. Soldering Information Ball Land Solder Mask Opening Table 11-6. Device and 247-ball BGA Package Maximum Weight 177 Table 11-7. 247-ball BGA Package Characteristics Moisture Sensitivity Level Table 11-8. Package Reference ...

Page 51

... SAM9G25 Ordering Information Table 12-1. SAM9G25 Ordering Information Ordering Code AT91SAM9G25-CU AT91SAM9G25-CFU 11032AS–ATARM–27-Jul-11 Package Package Type BGA217 Green BGA247 Green SAM9G25 Temperature Operating Range Industrial -40°C to 85°C Industrial -40°C to 85°C 51 ...

Page 52

SAM9G25 52 11032AS–ATARM–27-Jul-11 ...

Page 53

... Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, DataFlash®, SAM-BA® and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. ARM®, the ARMPowered® logo, Thumb® and others are the registered trademarks or trademarks of ARM Ltd ...

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