at91sam9g35-cu ATMEL Corporation, at91sam9g35-cu Datasheet

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at91sam9g35-cu

Manufacturer Part Number
at91sam9g35-cu
Description
At91sam Arm-based Embedded Mpu
Manufacturer
ATMEL Corporation
Datasheet

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Features
Core
Memories
System running at up to 133 MHz
Low Power Mode
Peripherals
I/O
Package
– ARM926EJ-S™ ARM
– 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit
– One 64-Kbyte internal ROM embedding bootstrap routine: Boot on NAND Flash,
– One 32-Kbyte internal SRAM, single-cycle access at system speed
– High Bandwidth Multi-port DDR2 Controller
– 32-bit External Bus Interface supporting 8-bank DDR2/LPDDR, SDR/LPSDR, Static
– MLC/SLC NAND Controller, with up to 24-bit Programmable Multi-bit Error
– Power-on Reset Cells, Reset Controller, Shut Down Controller, Periodic Interval
– Boot Mode Select Option, Remap Command
– Internal Low Power 32 kHz RC and Fast 12 MHz RC Oscillators
– Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator
– One PLL for the system and one PLL at 480 MHz optimized for USB High Speed
– Twelve 32-bit-layer AHB Bus Matrix for large Bandwidth transfers
– Dual Peripheral Bridge with dedicated programmable clock for best performance
– Two dual port 8-channel DMA Controller
– Advanced Interrupt Controller and Debug Unit
– Two Programmable External Clock Signals
– Shut Down Controller with four 32-bit Battery Backup Registers
– Clock Generator and Power Management Controller
– Very Slow Clock Operating Mode, Software Programmable Power Optimization
– LCD Controller with overlay, alpha-blending, rotation, scaling and color conversion
– USB Device High Speed, USB Host High Speed and USB Host Full Speed with
– One 10/100 Mbps Ethernet MAC Controller
– Two High Speed Memory Card Hosts
– Two Master/Slave Serial Peripheral Interface
– Two Three-channel 32-bit Timer/Counters
– One Synchronous Serial Controller
– One Four-channel 16-bit PWM Controller
– Three Two-wire Interfaces
– Three USARTs, two UARTs
– One 12-channel 10-bit Touch-Screen Analog-to-Digital Converter
– Soft Modem
– Four 32-bit Parallel Input/Output Controllers
– 105 Programmable I/O Lines Multiplexed with up to Three Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line, optional Schmitt trigger input
– Individually Programmable Open-drain, Pull-up and pull-down resistor,
– 217-ball BGA, pitch 0.8 mm
SDCard, DataFlash
Memories
Correcting Code (PMECC)
Timer, Watchdog Timer and Real Time Clock
Capabilities
dedicated On-Chip Transceiver
Synchronous Output
®
®
or serial DataFlash. Programmable order.
Thumb
®
Processor running at up to 400 MHz @ 1.0V +/- 10%
AT91SAM
ARM-based
Embedded MPU
SAM9G35
Summary
NOTE: This is a summary document.
The complete document is available on
the Atmel website at www.atmel.com.
11053AS–ATARM–27-Jul-11

Related parts for at91sam9g35-cu

at91sam9g35-cu Summary of contents

Page 1

Features • Core ® – ARM926EJ-S™ ARM Thumb – 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit • Memories – One 64-Kbyte internal ROM embedding bootstrap routine: Boot on NAND Flash, ® SDCard, DataFlash or serial DataFlash. ...

Page 2

Description The SAM9G35 is a member of the Atmel series of 400 MHz ARM926 embedded MPUs that sup- port high bandwidth communication and advanced user interfaces and are optimized for industrial applications such as building automation, data loggers, POS ...

Page 3

Block Diagram Figure 2-1. SAM9G35 Block Diagram 11053AS–ATARM–27-Jul-11 PIO PIO SAM9G35 3 ...

Page 4

Signal Description Table 3-1 Table 3-1. Signal Description List Signal Name Function XIN Main Oscillator Input XOUT Main Oscillator Output XIN32 Slow Clock Oscillator Input XOUT32 Slow Clock Oscillator Output VBG Bias Voltage Reference for USB PCK0-PCK1 Programmable Clock ...

Page 5

Table 3-1. Signal Description List (Continued) Signal Name Function D0-D15 Data Bus D16-D31 Data Bus A0-A25 Address Bus NWAIT External Wait Signal NCS0-NCS5 Chip Select Lines NWR0-NWR3 Write Signal NRD Read Signal NWE Write Enable NBS0-NBS3 Byte Mask Signal NFD0-NFD16 ...

Page 6

Table 3-1. Signal Description List (Continued) Signal Name Function Universal Synchronous Asynchronous Receiver Transmitter - USARTx SCKx USARTx Serial Clock TXDx USARTx Transmit Data RXDx USARTx Receive Data RTSx USARTx Request To Send CTSx USARTx Clear To Send UTXDx UARTx ...

Page 7

Table 3-1. Signal Description List (Continued) Signal Name Function PWM0-PWM3 Pulse Width Modulation Output HFSDPA USB Host Port A Full Speed Data + HFSDMA USB Host Port A Full Speed Data - HHSDPA USB Host Port A High Speed Data ...

Page 8

Table 3-1. Signal Description List (Continued) Signal Name Function AD0 Top/Upper Left Channel XP_UL AD1 Bottom/Upper Right Channel XM_UR AD2 Right/Lower Left Channel YP_LL AD3 Left/Sense Channel YM_SENSE AD4 Lower Right Channel LR AD5-AD11 7 Analog Inputs ADTRG ADC Trigger ...

Page 9

Package and Pinout The SAM9G35 is available in 217-ball BGA package. 4.1 Overview of the 217-ball BGA Package Figure 4-1 Figure 4-1. 4.2 I/O Description Table 4-1. I/O Type GPIO GPIO_CLK GPIO_CLK2 GPIO_ANA EBI EBI_O EBI_CLK RSTJTAG SYSC VBG ...

Page 10

When “Reset State” is mentioned, the configuration is defined by the “Reset State” column of the Pin Description table. Table 4-2. I/O Type GPIO GPIO_CLK GPIO_CLK2 GPIO_ANA EBI EBI_O EBI_CLK RSTJTAG SYSC VBG USBFS USBHS CLOCK DIB 4.2.1 Reset State ...

Page 11

Indicates if Schmitt Trigger is enabled. Note: 4.3 217-ball BGA Package Pinout Table 4-3. Pin Description BGA217 Ball Power Rail I/O Type Signal L3 VDDIOP0 GPIO P1 VDDIOP0 GPIO L4 VDDIOP0 GPIO N4 VDDIOP0 GPIO T3 VDDIOP0 GPIO ...

Page 12

Table 4-3. Pin Description BGA217 (Continued) Ball Power Rail I/O Type Signal D2 VDDANA GPIO PB2 E4 VDDANA GPIO PB3 D1 VDDANA GPIO_CLK PB4 E3 VDDANA GPIO PB5 B3 VDDANA GPIO_ANA PB6 C2 VDDANA GPIO_ANA PB7 C5 VDDANA GPIO_ANA PB8 ...

Page 13

Table 4-3. Pin Description BGA217 (Continued) Ball Power Rail I/O Type Signal P2 VDDIOP1 GPIO PC26 M1 VDDIOP1 GPIO PC27 K4 VDDIOP1 GPIO PC28 N1 VDDIOP1 GPIO_CLK PC29 R2 VDDIOP1 GPIO_CLK2 PC30 N2 VDDIOP1 GPIO PC31 P13 VDDNF EBI PD0 ...

Page 14

Table 4-3. Pin Description BGA217 (Continued) Ball Power Rail I/O Type Signal T13 VDDOSC POWER VDDOSC U13 GNDOSC GND GNDOSC H14, K8, VDDCORE POWER VDDCORE K9 H8, J8, GNDCORE GND GNDCORE K10 U16 VDDUTMII POWER VDDUTMII T17 VDDUTMIC POWER VDDUTMIC ...

Page 15

Table 4-3. Pin Description BGA217 (Continued) Ball Power Rail I/O Type Signal B17 VDDIOM EBI_O E15 VDDIOM EBI_O E14 VDDIOM EBI_O B9 VDDIOM EBI_O NCS0 B8 VDDIOM EBI_O NCS1 D9 VDDIOM EBI_O NRD C9 VDDIOM EBI_O NWR0 C7 VDDIOM EBI_O ...

Page 16

Table 4-3. Pin Description BGA217 (Continued) Ball Power Rail I/O Type Signal R10 VDDIOP0 RSTJTAG RTCK P10 VDDIOP0 RSTJTAG NRST T11 VDDIOP0 RSTJTAG NTRST A6 VDDBU CLOCK XIN32 A5 VDDBU CLOCK XOUT32 T12 VDDOSC CLOCK XIN U12 VDDOSC CLOCK XOUT ...

Page 17

Power Considerations 5.1 Power Supplies The SAM9G35 has several types of power supply pins. Table 5-1. SAM9G35 Power Supplies Name Voltage Range, nominal VDDCORE 0.9-1.1V, 1.0V 1.65-1.95V, 1.8V VDDIOM 3.0-3.6V, 3.3V 1.65-1.95V, 1.8V VDDNF 3.0-3.6V, 3.3V VDDIOP0 1.65-3.6V VDDIOP1 ...

Page 18

Processor and Architecture 6.1 ARM926EJ-S Processor • RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration • Two Instruction Sets – ARM High-performance 32-bit Instruction Set – Thumb High Code Density 16-bit Instruction Set • ...

Page 19

APB/AHB Bridge The SAM9G35 product embeds two separated APB/AHB bridges. This architecture enables to make concurrent access on both bridge. Each peripheral can be clocked at a lower speed (MCK divided clock) in order to decrease the current consumption. ...

Page 20

Matrix Masters The Bus Matrix of the SAM9G35 product manages 12 masters, which means that each master can perform an access concurrently with others available slave. Each master has its own decoder, which is defined specifically for ...

Page 21

Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the USB Device High speed DMA to the Internal Peripherals. Thus, these paths are ...

Page 22

DMA Controller 0 • Two Masters • Embeds 8 channels • 64-byte FIFO for channel 0, 16-byte FIFO for Channel • features: – Linked List support with Status Write Back operation at End of Transfer – ...

Page 23

DMA Controller 1 • Two Masters • Embeds 8 channels • 16-byte FIFO per Channel • features: – Linked List support with Status Write Back operation at End of Transfer – Word, HalfWord, Byte transfer support. – Peripheral to ...

Page 24

Debug and Test Features • ARM926 Real-time In-circuit Emulator – Two real-time Watchpoint Units – Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug ...

Page 25

Memories Figure 7-1. SAM9G35 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1 DDR2/LPDDR SDR/LPSDR 0x2FFF FFFF 0x3000 0000 EBI Chip Select 2 ...

Page 26

Memory Mapping A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 ...

Page 27

Multiple device adaptability – Control signals programmable setup, pulse and hold time for each Memory Bank • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time • Slow Clock mode ...

Page 28

System Controller The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure ...

Page 29

Figure 8-1. SAM9G35 System Controller Block Diagram periph_irq[2..30] pit_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset SHDN WKUP XIN32 SLOW CLOCK XOUT32 OSC XIN 12MHz MAIN OSC XOUT UPLL PLLA periph_nreset periph_nreset periph_clk[2..3] ...

Page 30

Chip Identification • Chip ID: 0x819A_05A1 • Chip ID Extension: 1 • JTAG ID: 0x05B2_F03F • ARM926 TAP ID: 0x0792_603F 8.2 Backup Section The SAM9G35 features a Backup Section that embeds: • RC Oscillator • Slow Clock Oscillator • ...

Page 31

Peripherals 9.1 Peripheral Mapping As shown in space between the addresses 0xF000 0000 and 0xFFFF C000. Each User Peripheral is allocated 16 Kbytes of address space. 9.2 Peripheral Identifiers Table 9-1 for the control of the peripheral interrupt with ...

Page 32

Table 9-1. Instance 9.3 Peripheral Signal Multiplexing on I/O Lines The SAM9G35 features 4 PIO Controllers, PIOA, PIOB, PIOC and PIOD, which multiplex the I/O lines of the peripheral set. Each PIO Controller ...

Page 33

Embedded Peripherals 10.1 Serial Peripheral Interface (SPI) • Two SPIs • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with – Serial memories, such as DataFlash and 3-wire ...

Page 34

MSB- or LSB-first – Optional break generation and detection – by-16 over-sampling receiver frequency – Hardware handshaking RTS-CTS – Receiver time-out and transmitter timeguard – Optional Multi-drop Mode with address generation and detection – Optional Manchester ...

Page 35

Serial Synchronous Controller (SSC) • One SSC • Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I • Contains an independent receiver and transmitter and a common clock divider ...

Page 36

High Speed USB Host Port (UHPHS) • Compliant with EnhancedHCI Rev 1.0 Specification – Compliant with USB V2.0 High-speed and Full-speed Specification – Supports Both High-speed 480Mbps and Full-speed 12 Mbps USB devices • Compliant with OpenHCI Rev 1.0 ...

Page 37

LCD Controller (LCDC) • One Master • 266MHz input clock • 384-byte Asynchronous Output FIFO • One Background Layer • One High End Overlay Layer, YUV Full planar, 4.2.0, 4.2.2 packed • One Overlay RGB • One ...

Page 38

DMA (DMAC) • Two DMACs • DMAC0 is full featured and optimized for memory-to-memory transfers thanks to the 64-word FIFO on channel 0 • DMAC1 is optimized for peripheral-to-memory transfers, without PIP support • Acting as Two Matrix ...

Page 39

Pulse Width Modulation Controller (PWM) • 4 channels, one 32-bit counter per channel • Common clock generator, providing Thirteen Different Clocks – A Modulo n counter providing eleven clocks – Two independent Linear Dividers working on modulo n counter ...

Page 40

Mechanical Overview Figure 11-1. 217-ball BGA Package Drawing SAM9G35 40 11053AS–ATARM–27-Jul-11 ...

Page 41

Table 11-1. Device and 217-ball BGA Package Maximum Weight 450 Table 11-2. 217-ball BGA Package Characteristics Moisture Sensitivity Level Table 11-3. Package Reference JEDEC Drawing Reference JESD97 Classification Table 11-4. Soldering Information Ball Land Solder Mask Opening 11053AS–ATARM–27-Jul- ...

Page 42

... SAM9G35 Ordering Information Table 12-1. SAM9G35 Ordering Information Ordering Code AT91SAM9G35-CU SAM9G35 42 Package Package Type BGA217 Green Temperature Operating Range Industrial -40°C to 85°C 11053AS–ATARM–27-Jul-11 ...

Page 43

... Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, DataFlash®, SAM-BA® and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. ARM®, the ARMPowered® logo, Thumb® and others are the registered trademarks or trademarks of ARM Ltd ...

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