at91sam9263 ATMEL Corporation, at91sam9263 Datasheet
at91sam9263
Manufacturer Part Number
at91sam9263
Description
At91 Arm Thumb Microcontrollers
Manufacturer
ATMEL Corporation
Datasheet
1.AT91SAM9263.pdf
(1065 pages)
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Features
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Incorporates the ARM926EJ-S
Bus Matrix
Embedded Memories
Dual External Bus Interface (EBI0 and EBI1)
DMA Controller (DMAC)
Twenty Peripheral DMA Controller Channels (PDC)
LCD Controller
2D Graphics Accelerator
Image Sensor Interface
USB 2.0 Full Speed (12 Mbits per second) Host Double Port
USB 2.0 Full Speed (12 Mbits per second) Device Port
Ethernet MAC 10/100 Base-T
Fully-featured System Controller, including
– DSP Instruction Extensions, Jazelle
– 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer
– 220 MIPS at 200 MHz
– Memory Management Unit
– EmbeddedICE
– Mid-level Implementation Embedded Trace Macrocell
– Nine 32-bit-layer Matrix, Allowing a Total of 28.8 Gbps of On-chip Bus Bandwidth
– Boot Mode Select Option, Remap Command
– One 128 Kbyte Internal ROM, Single-cycle Access at Maximum Bus Matrix Speed
– One 80 Kbyte Internal SRAM, Single-cycle Access at Maximum Processor or Bus
– One 16 Kbyte Internal SRAM, Single-cycle Access at Maximum Bus Matrix Speed
– EBI0 Supports SDRAM, Static Memory, ECC-enabled NAND Flash and
– EBI1 Supports SDRAM, Static Memory and ECC-enabled NAND Flash
– Acts as one Bus Matrix Master
– Embeds 2 Unidirectional Channels with Programmable Priority, Address
– Supports Passive or Active Displays
– Up to 24 bits per Pixel in TFT Mode, Up to 16 bits per Pixel in STN Color Mode
– Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Supports Virtual
– Line Draw, Block Transfer, Polygon Fill, Clipping, Commands Queuing
– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
– 12-bit Data Interface for Support of High Sensibility Sensors
– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
– Dual On-chip Transceivers
– Integrated FIFOs and Dedicated DMA Channels
– On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM
– Media Independent Interface or Reduced Media Independent Interface
– 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
– Reset Controller, Shutdown Controller
– Twenty 32-bit Battery Backup Registers for a Total of 80 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
Matrix Speed
CompactFlash
Generation, Channel Buffering and Control
Screen Buffers
™
®
, Debug Communication Channel Support
™
ARM
®
Thumb
®
Technology for Java
®
Processor
™
®
Acceleration
AT91 ARM
Thumb
Microcontrollers
AT91SAM9263
Preliminary
6249D–ATARM–20-Dec-07
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