at91rm3400 ATMEL Corporation, at91rm3400 Datasheet - Page 101

• Manufacturer Part Number: at91rm3400
• Description: Atmel Advanced At91 Arm Microcontroller
• Manufacturer: ATMEL Corporation

Advanced Interrupt Controller (AIC)
Overview
1790A–ATARM–11/03
The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored
interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to
substantially reduce the software and real-time overhead in handling internal and external
interrupts.
The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request)
inputs of an ARM processor. Inputs of the AIC are either internal peripheral interrupts or exter-
nal interrupts coming from the product's pins.
The 8-level Priority Controller allows the user to define the priority for each interrupt source,
thus permitting higher priority interrupts to be serviced even if a lower priority interrupt is being
treated.
Internal interrupt sources can be programmed to be level sensitive or edge triggered. External
interrupt sources can be programmed to be positive-edge or negative-edge triggered or high-
level or low-level sensitive.
The fast forcing feature redirects any internal or external interrupt source to provide a fast
interrupt rather than a normal interrupt.
Important Features of the AIC are:
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Controls the Interrupt Lines (nIRQ and nFIQ) of an ARM
Thirty-two Individually Maskable and Vectored Interrupt Sources
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8-level Priority Controller
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Vectoring
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Protect Mode
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Fast Forcing
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General Interrupt Mask
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Source 0 is Reserved for the Fast Interrupt Input (FIQ)
Source 1 is Reserved for System Peripherals (ST, RTC, PMC, DBGU…)
Source 2 to Source 31 Control up to Thirty Embedded Peripheral Interrupts or
External Interrupts
Programmable Edge-triggered or Level-sensitive Internal Sources
Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
External Sources
Drives the Normal Interrupt of the Processor
Handles Priority of the Interrupt Sources 1 to 31
Higher Priority Interrupts Can Be Served During Service of Lower Priority Interrupt
Optimizes Interrupt Service Routine Branch and Execution
One 32-bit Vector Register per Interrupt Source
Interrupt Vector Register Reads the Corresponding Current Interrupt Vector
Easy Debugging by Preventing Automatic Operations when Protect ModeIs Are
Enabled
Permits Redirecting any Normal Interrupt Source on the Fast Interrupt of the
Processor
Provides Processor Synchronization on Events Without Triggering an Interrupt
®
Processor
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