at91rm3400 ATMEL Corporation, at91rm3400 Datasheet - Page 128

• Manufacturer Part Number: at91rm3400
• Description: Atmel Advanced At91 Arm Microcontroller
• Manufacturer: ATMEL Corporation

Functional Description
Operating Modes
Definition
Clock Definitions
Clock Generator
128
AT91RM3400
The following operating modes are supported by the PMC and offer different power con-
sumption levels and event response latency times:
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The Power Management Controller provides the following clocks:
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The Clock Generator embeds:
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The Clock Generator integrates as an option a divider by 2. The ARM7-based systems
generally embed PLLs able to output between 20 MHz and 100 MHz and do not embed
the divider by 2. The ARM9-based systems generally embed PLLs able to output
between 80 MHz and 240 MHz. As the 48 MHz required by the USB cannot be reached
by such a PLL, the optional divider by 2 is implemented.
The block diagram of the Clock Generator is shown in Figure 36.
Normal Mode: The ARM processor clock is enabled and peripheral clocks are
enabled depending on application requirements.
Idle Mode: The ARM processor clock is disabled and waiting for the next interrupt
(or a main reset). The peripheral clocks are enabled depending on application
requirements. PDC transfers are still possible.
Slow Clock Mode: Slow clock mode is similar to normal mode, but the main
oscillator and the PLL are switched off to save power and the processor and the
peripherals run in Slow Clock mode. Note that slow clock mode is the mode
selected after the reset.
Standby Mode: Standby mode is a combination of Slow Clock mode and Idle Mode.
It enables the processor to respond quickly to a wake-up event by keeping power
consumption very low.
Slow Clock (SLCK), typically at 32.768 kHz, is the only permanent clock within the
system.
Master Clock (MCK), programmable from a few hundred Hz to the maximum
operating frequency of the device. It is available to the modules running
permanently, such as the AIC and the Memory Controller.
Processor Clock (PCK), typically the Master Clock for ARM7-based systems and a
faster clock on ARM9-based systems, switched off when entering idle mode.
Peripheral Clocks, typically MCK, provided to the embedded peripherals (USART,
SSC, SPI, TWI, TC, MCI, etc.) and independently controllable. In order to reduce the
number of clock names in a product, the Peripheral Clocks are named MCK in the
product datasheet.
UDP Clock (UDPCK), typically at 48 MHz, required by the USB Device Port
operations.
UHP Clock (UHPCK), typically at 48 MHz, required by the USB Host Port
operations.
Programmable Clock Outputs (PCK0 to PCK3) can be selected from the clocks
provided by the clock generator and driven on the PCK0 to PCK3 pins.
the Slow Clock Oscillator
the Main Oscillator
two PLL and divider blocks, A and B
1790A–ATARM–11/03