at91rm3400 ATMEL Corporation, at91rm3400 Datasheet - Page 229

• Manufacturer Part Number: at91rm3400
• Description: Atmel Advanced At91 Arm Microcontroller
• Manufacturer: ATMEL Corporation

Serial Peripheral Interface (SPI)
Overview
1790A–ATARM–11/03
The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides
communication with external devices in Master or Slave Mode. It also allows communication
between processors if an external processor is connected to the system.
The Serial Peripheral Interface is a shift register that serially transmits data bits to other SPIs.
During a data transfer, one SPI system acts as the master that controls the data flow, while the
other system acts as the slave, having data shifted into and out of it by the master. Different
CPUs can take turn being masters (Multiple Master Protocol versus Single Master Protocol
where one CPU is always the master while all of the others are always slaves), and one mas-
ter may simultaneously shift data into multiple slaves. However, only one slave may drive its
output to write data back to the master at any given time.
A slave device is selected when the master asserts its NSS signal. If multiple slave devices
exist, the master generates a separate slave select signal for each slave (NPCS).
The SPI system consists of two data lines and two control lines:
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The main features of the SPI are:
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Master Out Slave In (MOSI): This data line supplies the output data from the master
shifted into the input(s) of the slave(s).
Master In Slave Out (MISO): This data line supplies the output data from a slave to the
input of the master. There may be no more than one slave transmitting data during any
particular transfer.
Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the
data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles
once for each bit that is transmitted.
Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.
Supports Communication with Serial External Devices
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Master or Slave Serial Peripheral Bus Interface
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Connection to PDC Channel Capabilities Optimizes Data Transfers
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4 Chip Selects with External Decoder Support Allow Communication with Up to 15
Peripherals
Serial Memories, such as DataFlash and 3-wire EEPROMs
Serial Peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
Sensors
External Co-processors
8- to 16-bit Programmable Data Length Per Chip Select
Programmable Phase and Polarity Per Chip Select
Programmable Transfer Delays Between Consecutive Transfers and Between
Clock and Data Per Chip Select
Programmable Delay Between Consecutive Transfers
Selectable Mode Fault Detection
One Channel for the Receiver, One Channel for the Transmitter
Next Buffer Support
AT91RM3400
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