at91rm3400 ATMEL Corporation, at91rm3400 Datasheet - Page 278

• Manufacturer Part Number: at91rm3400
• Description: Atmel Advanced At91 Arm Microcontroller
• Manufacturer: ATMEL Corporation

Receiver Operations
Figure 99. Receiver Status
Parity
278
Baud Rate
US_RHR
AT91RM3400
RXRDY
US_CR
OVRE
Clock
Write
Read
RXD
Start
Bit
D0
Figure 98. Synchronous Mode Character Reception
When a character reception is completed, it is transferred to the Receive Holding Register
(US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is com-
pleted while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is
transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing
the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1.
The USART supports five parity modes selected by programming the PAR field in the Mode
Register (US_MR). The PAR field also enables the Multidrop mode, which is discussed in a
separate paragraph. Even and odd parity bit generation and error detection are supported.
If even parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a
number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. Accordingly,
the receiver parity checker counts the number of received 1s and reports a parity error if the
sampled parity bit does not correspond. If the odd parity is selected, the parity generator of the
transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1
if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of
received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark
parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters.
The receiver parity checker reports an error if the parity bit is sampled at 0.If the space parity is
used, the parity generator of the transmitter drives the parity bit at 0 for all characters. The
receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled, the
transmitter does not generate any parity bit and the receiver does not report any parity error.
D1
Example: 8-bit, Parity Enabled 1 Stop
Baud Rate
D2
Sampling
D3
Clock
RXD
D4
D5
D6
Start
D7
Parity
Bit
D0
Stop
Bit
Start
Bit
D1
D0
D1
D2
D2
D3
D3
D4
D5
D4
D6
D7
D5
Parity
Bit
Stop
Bit
D6
RSTSTA = 1
D7
Parity Bit
1790A–ATARM–11/03
Stop Bit