at91rm3400 ATMEL Corporation, at91rm3400 Datasheet - Page 279

• Manufacturer Part Number: at91rm3400
• Description: Atmel Advanced At91 Arm Microcontroller
• Manufacturer: ATMEL Corporation

Multi-drop Mode
1790A–ATARM–11/03
Table 48 shows an example of the parity bit for the character 0x41 (character ASCII “A”)
depending on the configuration of the USART. Because there are two bits at 1, 1 bit is added
when a parity is odd, or 0 is added when a parity is even. I
Table 48. Parity Bit Examples
When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Sta-
tus Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR)
with the RSTSTA bit at 1. Figure 100 illustrates the parity bit status setting and clearing.
Figure 100. Parity Error
If the PAR field in the Mode Register (US_MR) is programmed to the value 0x3, the USART
runs in Multi-drop mode. This mode differentiates the data characters and the address charac-
ters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit
at 1.
If the USART is configured in multi-drop mode, the receiver sets the PARE parity error bit
when the parity bit is high and the transmitter is able to send a character with the parity bit high
when the Control Register is written with the SENDA bit at 1.
To handle parity error, the PARE bit is cleared when the Control Register is written with the bit
RSTSTA at 1.
The transmitter sends an address byte (parity bit set) when SENDA is written to US_CR. In
this case, the next byte written to US_THR is transmitted as an address. Any character written
in US_THR without having written the command SENDA is transmitted normally with the parity
at 0.
Character
A
A
A
A
A
Baud Rate
RXRDY
US_CR
PARE
Clock
Write
RXD
Start
Bit
Hexa
0x41
0x41
0x41
0x41
0x41
D0
D1
D2
D3
D4
0100 0001
0100 0001
0100 0001
0100 0001
0100 0001
Binary
D5
D6
D7
Parity
Bad
Bit
Stop
Bit
Parity Bit
None
1
0
1
0
AT91RM3400
RSTSTA = 1
ParityMode
Space
None
Even
Mark
Odd
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