at91rm3400 ATMEL Corporation, at91rm3400 Datasheet - Page 286

• Manufacturer Part Number: at91rm3400
• Description: Atmel Advanced At91 Arm Microcontroller
• Manufacturer: ATMEL Corporation

Protocol T = 0
Figure 109. T = 0 Protocol without Parity Error
Figure 110. T = 0 Protocol with Parity Error
Receive Error Counter
Receive NACK Inhibit
Transmit Character
Repetition
286
Baud Rate
Baud Rate
Clock
I/O
AT91RM3400
Clock
RXD
Start
Bit
Start
Bit
D0
In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one
guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the
I/O line during the guard time.
If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter
can continue with the transmission of the next character, as shown in Figure 109.
If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as
shown in Figure 110. This error bit is also named NACK, for Non Acknowledge. In this case,
the character lasts 1 bit time more, as the guard time length is the same and is added to the
error bit time which lasts 1 bit time.
When the USART is the receiver and it detects an error, it does not load the erroneous charac-
ter in the Receive Holding Register (US_RHR). It appropriately sets the PARE bit in the Status
Register (US_SR) so that the software can handle the error.
The USART receiver also records the total number of errors. This can be read in the Number
of Error (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading
US_NER automatically clears the NB_ERRORS field.
The USART can also be configured to inhibit an error. This can be achieved by setting the
INACK bit in the Mode Register (US_MR). If INACK is at 1, no error signal is driven on the I/O
line even if a parity bit is detected, but the INACK bit is set in the Status Register (US_SR).
The INACK bit can be cleared by writing the Control Register (US_CR) with the RSTNACK bit
at 1.
Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding
Register, as if no error occurred. However, the RXRDY bit does not raise.
When the USART is transmitting a character and gets a NACK, it can automatically repeat the
character before moving on to the next one. Repetition is enabled by writing the
MAX_ITERATION field in the Mode Register (US_MR) at a value higher than 0. Each charac-
ter can be transmitted up to eight times; the first transmission plus seven repetitions.
If MAX_ITERATION does not equal zero, the USART repeats the character as many times as
the value loaded in MAX_ITERATION.
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
Parity
Bit
Parity
Bit
Time 1
Guard
Time 1
Guard
Error
Time 2
Guard
Time 2
Guard
Next
Start
Bit
Start
Bit
1790A–ATARM–11/03
Repetition
D0
D1