at91rm3400 ATMEL Corporation, at91rm3400 Datasheet - Page 315

• Manufacturer Part Number: at91rm3400
• Description: Atmel Advanced At91 Arm Microcontroller
• Manufacturer: ATMEL Corporation

Clock
Management
Clock Divider
1790A–ATARM–11/03
The transmitter clock can be generated by:
•
•
•
The receiver clock can be generated by:
•
•
•
Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the
receiver block can generate an external clock on the RK I/O pad.
This allows the SSC to support many Master and Slave-mode data transfers.
Figure 123. Divided Clock Block Diagram
The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its
maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock divi-
sion by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When
this field is programmed to 0, the Clock Divider is not used and remains inactive.
When DIV is set to a value equal or greater to 1, the Divided Clock has a frequency of Master
Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the Master
Clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless if the
DIV value is even or odd.
Figure 124. Divided Clock Generation
Table 56. Bit Rate
Maximum
MCK / 2
an external clock received on the TK I/O pad
the receiver clock
the internal clock divider
an external clock received on the RK I/O pad
the transmitter clock
the internal clock divider
Divided Clock
Divided Clock
Master Clock
Master Clock
DIV = 3
DIV = 1
MCK
/ 2
Divided Clock Frequency = MCK/2
Divided Clock Frequency = MCK/6
Clock Divider
12-bit Counter
Minimum
MCK / 8190
SSC_CMR
Divided Clock
AT91RM3400
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