at91rm3400 ATMEL Corporation, at91rm3400 Datasheet - Page 329

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at91rm3400

Manufacturer Part Number
at91rm3400
Description
Atmel Advanced At91 Arm Microcontroller
Manufacturer
ATMEL Corporation
Datasheet

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AT91RM3400
• STTDLY: Receive Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception.
When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied.
Please Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG
(Receive Sync Data) reception.
• PERIOD: Receive Period Divider Selection
This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no
PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock.
329
1790A–ATARM–11/03

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