lpc1759

Manufacturer Part Numberlpc1759
DescriptionLpc17xx Device Highlight
ManufacturerNXP Semiconductors
lpc1759 datasheet
 


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LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 MCU; up to 512 kB flash and 64 kB
SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN
Rev. 04.02 — 1 April 2010
1. General description
The LPC1759/58/56/54/52/51 are ARM Cortex-M3 based microcontrollers for embedded
applications featuring a high level of integration and low power consumption. The ARM
Cortex-M3 is a next generation core that offers system enhancements such as enhanced
debug features and a higher level of support block integration.
The LPC1758/56/57/54/52/51 operate at CPU frequencies of up to 100 MHz. The
LPC1759 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU
incorporates a 3-stage pipeline and uses a Harvard architecture with separate local
instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3
CPU also includes an internal prefetch unit that supports speculative branching.
The peripheral complement of the LPC1759/58/56/54/52/51 includes up to 512 kB of flash
memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface,
8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers,
SPI interface, 2 I
12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, 4 general
purpose timers, 6-output general purpose PWM, ultra-low power Real-Time Clock (RTC)
with separate battery supply, and up to 52 general purpose I/O pins.
2. Features and benefits
ARM Cortex-M3 processor, running at frequencies of up to 100 MHz
(LPC1758/56/57/54/52/51) or of up to 120 MHz (LPC1759). A Memory Protection Unit
(MPU) supporting eight regions is included.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator
enables high-speed 120 MHz operation with zero wait states.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
On-chip SRAM includes:
Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance
CPU access.
Two/one 16 kB SRAM blocks with separate access paths for higher throughput.
These SRAM blocks may be used for Ethernet (LPC1758 only), USB, and DMA
memory, as well as for general purpose CPU instruction and data storage.
Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer
matrix that can be used with the SSP, I
Digital-to-Analog converter peripherals, timer match signals, and for
memory-to-memory transfers.
2
C-bus interfaces, 2-input plus 2-output I
2
S-bus, UART, the Analog-to-Digital and
Product data sheet
2
S-bus interface, 6 channel

lpc1759 Summary of contents

  • Page 1

    ... The LPC1758/56/57/54/52/51 operate at CPU frequencies 100 MHz. The LPC1759 operates at CPU frequencies 120 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching ...

  • Page 2

    ... Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support. CAN 2.0B controller with two (LPC1759/58/56) or one (LPC1754/52/51) channels. SPI controller with synchronous, serial, full duplex communication and programmable data length. ...

  • Page 3

    ... Available as 80-pin LQFP package (12 mm × × 1.4 mm). 3. Applications eMetering Lighting Industrial networking Alarm systems White goods Motor control LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller All information provided in this document is subject to legal disclaimers. Rev. 04.02 — 1 April 2010 © NXP B.V. 2010. All rights reserved ...

  • Page 4

    ... LPC1752FBD80 LQFP80 plastic low-profile quad package; 80 leads; body 12 × 12 × 1.4 mm LPC1751FBD80 LQFP80 4.1 Ordering options Table 2. Ordering options Type number Flash SRAM in kB CPU AHB SRAM0 LPC1759FBD80 512 LPC1758FBD80 512 LPC1756FBD80 256 LPC1754FBD80 128 LPC1752FBD80 LPC1751FBD80 ...

  • Page 5

    ... MULTILAYER AHB MATRIX slave slave AHB TO AHB TO APB APB BRIDGE 0 BRIDGE 1 RTC (1) LPC1759/58/56 only (3) LPC1759/58/56/54 only (2) LPC1758 only (4) LPC1752/51 USB device only All information provided in this document is subject to legal disclaimers. Rev. 04.02 — 1 April 2010 32-bit ARM Cortex-M3 microcontroller XTAL1 XTAL2 RESET CLOCK GENERATION, ...

  • Page 6

    ... P0[6] — General purpose digital input/output pin. I2SRX_SDA — Receive data driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I (LPC1759/58/56 only). SSEL1 — Slave Select for SSP1. MAT2[0] — Match output for Timer 2, channel 0. All information provided in this document is subject to legal disclaimers. ...

  • Page 7

    ... DCD1 — Data Carrier Detect input for UART1. MOSI0 — Master Out Slave In for SSP0. MOSI — Master Out Slave In for SPI. All information provided in this document is subject to legal disclaimers. Rev. 04.02 — 1 April 2010 2 S-bus specification. 2 S-bus specification. (LPC1759/58/56 2 S-bus specification. © NXP B.V. 2010. All rights reserved ...

  • Page 8

    ... TXD3 — Transmitter output for UART3. P0[26] — General purpose digital input/output pin. AD0[3] — A/D converter 0, input 3. AOUT — DAC output. (LPC1759/58/56/54 only). RXD3 — Receiver input for UART3. P0[29] — General purpose digital input/output pin. USB_D+ — USB bidirectional D+ line. ...

  • Page 9

    ... Description P1[19] — General purpose digital input/output pin. MCOA0 — Motor control PWM channel 0, output A. USB_PPWR — Port Power enable signal for USB port. (LPC1759/58/56/54 only). CAP1[1] — Capture input for Timer 1, channel 1. P1[20] — General purpose digital input/output pin. MCI0 — Motor control PWM channel 0, input. Also Quadrature Encoder Interface PHA input. PWM1[2] — ...

  • Page 10

    ... RI1 — Ring Indicator input for UART1. TRACECLK — Trace Clock. P2[7] — General purpose digital input/output pin. RD2 — CAN2 receiver input. (LPC1759/58/56 only). RTS1 — Request to Send output for UART1. Can also be configured RS-485/EIA-485 output enable signal. All information provided in this document is subject to legal disclaimers. ...

  • Page 11

    ... LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller Description P2[8] — General purpose digital input/output pin. TD2 — CAN2 transmitter output. (LPC1759/58/56 only). TXD2 — Transmitter output for UART2. P2[9] — General purpose digital input/output pin. USB_CONNECT — Signal used to switch an external 1.5 kΩ resistor under software control. Used with the SoftConnect USB feature. ...

  • Page 12

    ... XTAL2 should be left floating. [11] When the RTC is not used, connect VBAT to V LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller Description analog ground reference. This should nominally be the same voltage as V but should be isolated to minimize noise and error. ...

  • Page 13

    ... AHB-Lite buses. 7.4 On-chip SRAM The LPC1759/58/56/54/52/51 contain a total on-chip static RAM memory. This includes the main 32/16/8 kB SRAM, accessible by the CPU and DMA controller on a higher-speed bus, and up to two additional 16 kB each SRAM blocks situated on a separate slave port on the AHB multilayer matrix ...

  • Page 14

    ... Accesses to memory locations that are not defined in the MPU regions, or not permitted by the region setting, will cause the Memory Management Fault exception to take place. 7.6 Memory map The LPC1759/58/56/54/52/51 incorporate several distinct memory regions, shown in the following figures. user program viewpoint following reset. The interrupt vector area supports address remapping. ...

  • Page 15

    ... GB 0x2007 C000 reserved 0x1FFF 2000 8 kB boot ROM 0x1FFF 0000 reserved 0x1000 8000 32 kB local static RAM (LPC1759/8) 0x1000 4000 16 kB local static RAM (LPC1756/4/2) 0x1000 2000 8 kB local static RAM (LPC1751) 0x1000 0000 reserved 0x0008 0000 512 kB on-chip flash (LPC1759/8) ...

  • Page 16

    ... The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.7.1 Features • Controls system exceptions and peripheral interrupts • In the LPC1759/58/56/54/52/51, the NVIC supports 33 vectored interrupts • 32 programmable interrupt priority levels, with hardware priority level masking • Relocatable vector table • ...

  • Page 17

    ... The value of the output register may be read back as well as the current state of the port pins. LPC1759/58/56/54/52/51 use accelerated GPIO functions: • GPIO registers are accessed through the AHB multilayer bus so that the fastest possible I/O timing can be achieved. • ...

  • Page 18

    ... DMA managers with scatter/gather DMA and arrays of frame descriptors. – Memory traffic optimized by buffering and pre-fetching. • Enhanced Ethernet features: LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller All information provided in this document is subject to legal disclaimers. Rev. 04.02 — 1 April 2010 © NXP B.V. 2010. All rights reserved ...

  • Page 19

    ... All transactions are initiated by the host controller. The LPC1759/58/56/54 USB interface includes a device, Host, and OTG controller with on-chip PHY for device and Host functions. The OTG switching protocol is supported through the use of an external controller. Details on typical USB interfacing solutions can ...

  • Page 20

    ... NXP Semiconductors • While USB is in the Suspend mode, the LPC1759/58/56/54/52/51 can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints. • Allows dynamic switching between CPU-controlled slave and DMA modes. ...

  • Page 21

    ... Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • FullCAN messages can generate interrupts. 7.14 12-bit ADC The LPC1759/58/56/54/52/51 contain one ADC single 12-bit successive approximation ADC with six channels and DMA support. 7.14.1 Features • 12-bit successive approximation ADC. ...

  • Page 22

    ... All UARTs have DMA support. 7.17 SPI serial I/O controller The LPC1759/58/56/54/52/51 contain one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer ...

  • Page 23

    ... DMA transfers supported by GPDMA 2 7.19 I C-bus serial I/O controllers The LPC1759/58/56/54/52/51 each contain two I 2 The I C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line (SCL) and a Serial Data Line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e ...

  • Page 24

    ... Controls include reset, stop and mute options separately for I 7.21 General purpose 32-bit timers/external event counters The LPC1759/58/56/54/52/51 include four 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers ...

  • Page 25

    ... Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC1759/58/56/54/52/51. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers ...

  • Page 26

    ... Digital filter with programmable delays for encoder input signals. • Can accept decoded signal inputs (clk and direction). • Connected to APB. LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller All information provided in this document is subject to legal disclaimers. Rev. 04.02 — 1 April 2010 © NXP B.V. 2010. All rights reserved ...

  • Page 27

    ... ARM Cortex-M3 system tick timer The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception interval. In the LPC1759/58/56/54/52/51, this timer can be clocked from the internal AHB clock or from a device pin. 7.27 Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘ ...

  • Page 28

    ... RTC and backup registers The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. The RTC on the LPC1759/58/56/54/52/51 is designed to have extremely low power consumption, i.e. less than 1 μA. The RTC will typically run from the main chip power supply, conserving battery power while the rest of the device is powered up ...

  • Page 29

    ... PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC1759/58/56/54/52/51 use the IRC as the clock source. Software may later switch to one of the other available clock sources. ...

  • Page 30

    ... PLL0, wait for the PLL0 to lock, and then connect to the PLL0 as a clock source. 7.29.3 USB PLL (PLL1) The LPC1759/58/56/54/52/51 contain a second, dedicated USB PLL1 to provide clocking for the USB interface. The PLL1 receives its clock input from the main oscillator only and provides a fixed 48 MHz clock to the USB block only ...

  • Page 31

    ... Power control The LPC1759/58/56/54/52/51 support a variety of power control features. There are four special modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value ...

  • Page 32

    ... The Deep power-down mode can only be entered from the RTC block. In Deep power-down mode, power is shut off to the entire chip with the exception of the RTC module and the RESET pin. The LPC1759/58/56/54/52/51 can wake up from Deep power-down mode via the RESET pin or an alarm match event of the RTC. 7.29.5.5 Wakeup interrupt controller ...

  • Page 33

    ... NXP Semiconductors On the LPC1759/58/56/54/52/51, I/O pads are powered by the 3 the V DD(REG)(3V3) the CPU and most of the peripherals. Depending on the LPC1759/58/56/54/52/51 application, a design can use two power options to manage power consumption. The first option assumes that power consumption is not a concern and the design ties the ...

  • Page 34

    ... Power distribution 7.30 System control 7.30.1 Reset Reset has four sources on the LPC1759/58/56/54/52/51: the RESET pin, the Watchdog reset, Power-On Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the ...

  • Page 35

    ... Code security (Code Read Protection - CRP) This feature of the LPC1759/58/56/54/52/51 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location ...

  • Page 36

    ... DMA controllers to the various peripheral functions. 7.30.6 External interrupt inputs The LPC1759/58/56/54/52/51 include edge sensitive interrupt inputs combined with one level sensitive external interrupt input as selectable pin function. The external interrupt input can optionally be used to wake up the processor from Power-down mode. ...

  • Page 37

    ... The peak current is limited to 25 times the corresponding maximum current. [5] Dependent on package type. [6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor. LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller [1] Conditions external rail for the RTC on ADC related ...

  • Page 38

    ... Thermal characteristics − ° 2 3 +85 DD amb Symbol Parameter T maximum junction j(max) temperature LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 (°C), can be calculated using the following J ( × – ° C unless otherwise specified; Conditions Min - All information provided in this document is subject to legal disclaimers. ...

  • Page 39

    ... CCLK PCLK = 8 [3][4] CCLK = 12 MHz; PLL - disabled [3][4] CCLK = 100 MHz; PLL - enabled [3][5] CCLK = 100 MHz; PLL enabled (LPC1759) [3][5] CCLK = 120 MHz; PLL - enabled (LPC1759) [3][6] Sleep mode - [3][7] Deep sleep mode - [3][7] Power-down mode - [3] Deep power-down mode; - RTC not running Deep power-down mode; RTC running [8] ...

  • Page 40

    ... XTAL1 V output voltage on pin o(XTAL2) XTAL2 V input voltage on pin i(RTCX1) RTCX1 V output voltage on pin o(RTCX2) RTCX2 LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller Conditions Min on pin VREFP [12] Deep sleep mode - [12] Power-down mode - [12] Deep power-down - mode = 0 V; on-chip pull-up ...

  • Page 41

    ... DD(REG)(3V3) amb [4] Applies to LPC1758, LPC1756, LPC1754, LPC1752, LPC1751. [5] Applies to LPC1759 only. [6] IRC running at 4 MHz; main oscillator and PLL disabled; PCLK = [7] BOD disabled. [8] On pin VBAT 520 nA. V DD(REG)(3V3 °C. ...

  • Page 42

    ... DD(Reg)(3V3) (μ −40 Conditions: V Fig 7. Power-down mode: Regulator supply current I LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller − 3.3 V; BOD disabled. DD(Reg)(3V3) − 3.3 V; BOD disabled. DD(Reg)(3V3) All information provided in this document is subject to legal disclaimers. ...

  • Page 43

    ... Conditions: V Fig 8. Deep power-down mode: Battery supply current I LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller − 3 floating; RTC not running. BAT DD(Reg)(3V3) All information provided in this document is subject to legal disclaimers. Rev. 04.02 — 1 April 2010 002aaf402 ...

  • Page 44

    ... (mA Conditions: V Fig 10. Typical LOW-level output current I LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller °C 25 °C −40 ° 3.3 V; standard port pins. DD(REG)(3V3) DD(3V3) versus HIGH-level output source current OH 0 3.3 V; standard port pins. ...

  • Page 45

    ... Fig 11. Typical pull-up current (μ −10 0 Conditions: V Fig 12. Typical pull-down current I LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/ °C 25 °C −40 ° 3.3 V; standard port pins. DD(REG)(3V3) DD(3V3) versus input voltage °C 25 °C −40 °C ...

  • Page 46

    ... Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. [2] Fig 13. External clock timing (with an amplitude of at least V LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller Conditions Min [1] 10000 ...

  • Page 47

    ... DD(3V3) Symbol Parameter t rise time r t fall time f [1] Applies to standard port pins and RESET pin. LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 ≤ [1] 3.6 V. Conditions Min - 3. −15 10 ≤ 3.6 V and T = −40 °C to +85 °C. Variations between parts may cause the IRC DD(3V3) ...

  • Page 48

    ... SCL, the data must be valid by the set-up time before it releases the clock. [ the data set-up time that is measured with respect to the rising edge of SCL; applies to data in SU;DAT transmission and the acknowledge. LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 2 [1] C-bus pins ° [2] C. Parameter ...

  • Page 49

    ... SDA HD;DAT SCL SCL 2 Fig 15. I C-bus pins clock timing LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 t SU;DAT HIGH LOW All information provided in this document is subject to legal disclaimers. Rev. 04.02 — 1 April 2010 32-bit ARM Cortex-M3 microcontroller t VD ...

  • Page 50

    ... NXP Semiconductors 2 11.6 I S-bus interface (LPC1759/58/56 only) Table 12. Dynamic characteristics: I − ° ° +85 C. amb Symbol Parameter common to input and output t rise time r t fall time f t pulse width HIGH WH t pulse width LOW WL output t data output valid time ...

  • Page 51

    ... NXP Semiconductors I2SRX_CLK I2SRX_SDA I2SRX_WS 2 Fig 17. I S-bus timing (input) LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller T cy(clk su(D) t su(D) All information provided in this document is subject to legal disclaimers. Rev. 04.02 — 1 April 2010 h(D) 002aae159 t su(D) © NXP B.V. 2010. All rights reserved. ...

  • Page 52

    ... The peripheral clock for SSP is PCLK = CCLK = 20 MHz. shifting edges SCK MOSI MISO Fig 18. SSP MISO line set-up time in SPI Master mode LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller Conditions measured in SPI Master mode; see Figure 18 t su(SPI_MISO) All information provided in this document is subject to legal disclaimers. ...

  • Page 53

    ... PERIOD crossover point differential data lines differential data to SE0/EOP skew n × T PERIOD Fig 19. Differential data-to-EOP transition skew and EOP width LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller , unless otherwise specified. Conditions see Figure 19 ...

  • Page 54

    ... Timing parameters are measured with respect to the 50 % edge of the clock PCLK and the 10 % (90 %) edge of the data signal (MOSI or MISO). SCK (CPOL = 0) SCK (CPOL = 1) Fig 20. SPI master timing (CPHA = 1) LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller ° C. Min 10 [1] 79.6 × ...

  • Page 55

    ... NXP Semiconductors Fig 21. SPI master timing (CPHA = 0) SCK (CPOL = 0) SCK (CPOL = 1) Fig 22. SPI slave timing (CPHA = 1) LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 T SPICYC SCK (CPOL = 0) SCK (CPOL = 1) t SPIQV DATA VALID MOSI t DATA VALID MISO T SPICYC MOSI DATA VALID t SPIQV MISO DATA VALID All information provided in this document is subject to legal disclaimers. Rev. 04.02 — ...

  • Page 56

    ... T ADC and the ideal transfer curve. See [9] See Figure 25. [10] The conversion frequency corresponds to the number of samples per second. LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 T SPICYC SCK (CPOL = 0) SCK (CPOL = 1) MOSI DATA VALID t SPIQV MISO DATA VALID ° ...

  • Page 57

    ... G error, and the straight line which fits the ideal transfer curve. See [6] The conversion frequency corresponds to the number of samples per second. LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 Conditions [3][4] [5] [6] [7] 3.0 V ≤ V ≤ ...

  • Page 58

    ... Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. Fig 24. 12-bit ADC characteristics LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller (2) (1) (5) (4) (3) 1 LSB (ideal) 4090 4091 5 ...

  • Page 59

    ... NXP Semiconductors COMPARATOR The values of resistor components R process-dependent. Fig 25. ADC interface to pins AD0[n] 13. DAC electrical characteristics (LPC1759/58/56/54 only) Table 18. DAC electrical characteristics − ° 2 3 +85 DDA amb Symbol Parameter E differential linearity error D E integral non-linearity L(adj) E offset error ...

  • Page 60

    ... NXP Semiconductors 14. Application information 14.1 Suggested USB interface solutions LPC17xx Fig 26. LPC1759/58/56/54/52/51 USB interface on a self-powered device LPC17xx Fig 27. LPC1759/58/56/54/52/51 USB interface on a bus-powered device LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller V DD(3V3) USB_UP_LED USB_CONNECT SoftConnect switch R1 1.5 kΩ V BUS Ω ...

  • Page 61

    ... SCL1/2 56/54 SDA1/2 EINT0 USB_D+ USB_D− USB_UP_LED Fig 28. LPC1759/58/56/54 USB OTG port configuration USB_UP_LED USB_D+ USB_D− LPC1759/58/ 56/54 USB_PWRD USB_PPWR Fig 29. LPC1759/58/56/54 USB host port configuration LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/ RESET_N ADR/PSW OE_N/INT_N V DD SPEED ISP1302 SUSPEND SCL SDA ...

  • Page 62

    ... USB_D+ USB_D− V BUS Fig 30. LPC1759/58/56/54/52/51 USB device port configuration 14.2 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF ...

  • Page 63

    ... MHz - 10 MHz 10 MHz - 15 MHz 15 MHz - 20 MHz Table 20. Recommended values for C components parameters): high frequency mode Fundamental oscillation frequency F OSC 15 MHz - 20 MHz 20 MHz - 25 MHz LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller LPC1xxx XTALIN XTALOUT XTAL evaluation oscillation mode (crystal and external ...

  • Page 64

    ... Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of C accordingly to the increase in parasitics of the PCB layout. LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller LPC1xxx RTCX1 RTCX2 32 kHz XTAL ...

  • Page 65

    ... Fig 34. Standard I/O pin configuration with analog input LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller open-drain enable output enable data output pull-up enable repeater mode enable pull-down enable data input ...

  • Page 66

    ... NXP Semiconductors 14.6 Reset pin configuration reset Fig 35. Reset pin configuration LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller GLITCH FILTER All information provided in this document is subject to legal disclaimers. Rev. 04.02 — 1 April 2010 ESD PIN ESD ...

  • Page 67

    ... Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT315-1 136E15 Fig 36. Package outline (LQFP80) LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/ ...

  • Page 68

    ... RMII SE0 SPI SSI SSP TTL UART USB LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller Description Analog-to-Digital Converter Advanced High-performance Bus Advanced Microcontroller Bus Architecture Advanced Peripheral Bus BrownOut Detection Controller Area Network Digital-to-Analog Converter Debug Communication Channel ...

  • Page 69

    ... In Table 6 move parameter V value from typical to minimum. hys • Added part LPC1759. • Added SRAM sizes for CPU SRAM, AHB SRAM0, and AHB SRAM1 in • Added table note for XTAL1 and XTAL2 pins in • Changed minimum value of parameters V to −0.5 V. ...

  • Page 70

    ... Revision history …continued Document ID Modifications: LPC1758_56_54_52_51_2 Modifications: LPC1758_56_54_52_51_1 LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 Release date Data sheet status • Added Electrical pin characteristics (Section 10.1). • Changed data sheet status to Product. • Maximum data bit rate for SPI, SSP, UART added. • ...

  • Page 71

    ... LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. ...

  • Page 72

    ... Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: LPC1759_58_56_54_52_51_4 Product data sheet LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — ...

  • Page 73

    ... Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.12.2 USB host controller (LPC1759/58/56/54 only). 20 7.12.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.12.3 USB OTG controller (LPC1759/58/56/54 only 7.12.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.13 CAN controller and acceptance filters . . . . . . 20 7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.14 12-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.15 10-bit DAC (LPC1759/58/56/54 only 7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.16 UARTs 7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.17 SPI serial I/O controller 7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.18 SSP serial I/O controller . . . . . . . . . . . . . . . . . 22 7.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2 7.19 I C-bus serial I/O controllers ...

  • Page 74

    ... NXP Semiconductors 13 DAC electrical characteristics (LPC1759/58/56/54 only Application information 14.1 Suggested USB interface solutions . . . . . . . . 60 14.2 Crystal oscillator XTAL input and component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 14.3 RTC 32 kHz oscillator component selection . . 64 14.4 XTAL Printed-Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 14.5 Standard I/O pin configuration . . . . . . . . . . . . 65 14.6 Reset pin configuration . . . . . . . . . . . . . . . . . . 66 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 67 16 Abbreviations ...