lpc1759 NXP Semiconductors, lpc1759 Datasheet - Page 50

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lpc1759

Manufacturer Part Number
lpc1759
Description
Lpc17xx Device Highlight
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
Table 12.
T
[1]
LPC1759_58_56_54_52_51_4
Product data sheet
Symbol
common to input and output
t
t
t
t
output
t
input
t
t
r
f
WH
WL
v(Q)
su(D)
h(D)
amb
CCLK = 20 MHz; peripheral clock to the I
specification.
=
40
°
Dynamic characteristics: I
Parameter
rise time
fall time
pulse width HIGH
pulse width LOW
data output valid time
data input set-up time
data input hold time
C to +85
11.6 I
°
C.
2
Fig 16. I
S-bus interface (LPC1759/58/56 only)
I2STX_SDA
I2STX_CLK
I2STX_WS
2
S-bus timing (output)
2
Conditions
on pins I2STX_CLK and
I2SRX_CLK
on pins I2STX_CLK and
I2SRX_CLK
on pin I2STX_SDA;
on pin I2STX_WS
on pin I2SRX_SDA
on pin I2SRX_SDA
2
S-bus interface pins
S-bus interface PCLK =
All information provided in this document is subject to legal disclaimers.
Rev. 04.02 — 1 April 2010
t
WH
T
cy(clk)
CCLK
t
v(Q)
4
t
; T
v(Q)
LPC1759/58/56/54/52/51
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
cy(clk)
t
WL
Min
-
-
0.495 × T
-
-
-
3.5
4.0
= 1600 ns, corresponds to the SCK signal in the I
32-bit ARM Cortex-M3 microcontroller
cy(clk)
Typ
-
-
-
-
-
-
-
-
t
f
Max
35
35
-
0.505 × T
30
30
-
-
© NXP B.V. 2010. All rights reserved.
cy(clk)
t
r
002aad992
Unit
ns
ns
-
ns
ns
ns
ns
ns
50 of 74
2
S-bus

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